audio1ctl.vhd

ALTERA的语音芯片程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity audio1ctl is
	port(clk,over,reset:in std_logic;
		data:out std_logic_vector(23 downto 0);
		start:out std_logic);