audio.tan.rpt

ALTERA的语音芯片程序

    Info: Node "Add0~418"
    Info: Node "Add0~420"
    Info: Node "Add0~419"
    Info: Node "Add0~423"
    Info: Node "Add0~425"
    Info: Node "Add0~421"
    Info: Node "Add0~416"
    Info: Node "Mux3~56"
    Info: Node "sclk~114"
    Info: Node "Add0~412"
    Info: Node "Add0~410"
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 349.28 MHz between source register "sdo" and destination register "sdo" (period= 2.863 ns)
    Info: + Longest register to register delay is 2.649 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'
        Info: 2: + IC(0.486 ns) + CELL(0.438 ns) = 0.924 ns; Loc. = LCCOMB_X48_Y27_N4; Fanout = 1; COMB Node = 'Mux1~549'
        Info: 3: + IC(0.439 ns) + CELL(0.150 ns) = 1.513 ns; Loc. = LCCOMB_X47_Y27_N16; Fanout = 1; COMB Node = 'Mux1~550'
        Info: 4: + IC(0.254 ns) + CELL(0.271 ns) = 2.038 ns; Loc. = LCCOMB_X47_Y27_N20; Fanout = 1; COMB Node = 'Mux1~551'
        Info: 5: + IC(0.256 ns) + CELL(0.271 ns) = 2.565 ns; Loc. = LCCOMB_X47_Y27_N30; Fanout = 1; COMB Node = 'Mux1~561'
        Info: 6: + IC(0.000 ns) + CELL(0.084 ns) = 2.649 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'
        Info: Total cell delay = 1.214 ns ( 45.83 % )
        Info: Total interconnect delay = 1.435 ns ( 54.17 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.643 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.989 ns) + CELL(0.537 ns) = 2.643 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'
            Info: Total cell delay = 1.536 ns ( 58.12 % )
            Info: Total interconnect delay = 1.107 ns ( 41.88 % )
        Info: - Longest clock path from clock "clk" to source register is 2.643 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.989 ns) + CELL(0.537 ns) = 2.643 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'
            Info: Total cell delay = 1.536 ns ( 58.12 % )
            Info: Total interconnect delay = 1.107 ns ( 41.88 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "sdo" (data pin = "start", clock pin = "clk") is 12.146 ns
    Info: + Longest pin to register delay is 14.825 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 13; PIN Node = 'start'
        Info: 2: + IC(0.000 ns) + CELL(10.962 ns) = 11.941 ns; Loc. = LCCOMB_X46_Y27_N24; Fanout = 12; COMB LOOP Node = 'Add0~422'
            Info: Loc. = LCCOMB_X46_Y26_N16; Node "Add0~425"
            Info: Loc. = LCCOMB_X46_Y27_N18; Node "Add0~416"
            Info: Loc. = LCCOMB_X46_Y27_N20; Node "Add0~419"
            Info: Loc. = LCCOMB_X46_Y27_N18; Node "Add0~417"
            Info: Loc. = LCCOMB_X46_Y26_N30; Node "Mux3~56"
            Info: Loc. = LCCOMB_X46_Y27_N20; Node "Add0~418"
            Info: Loc. = LCCOMB_X46_Y26_N0; Node "Add0~413"
            Info: Loc. = LCCOMB_X46_Y27_N24; Node "Add0~422"
            Info: Loc. = LCCOMB_X46_Y27_N16; Node "Add0~415"
            Info: Loc. = LCCOMB_X46_Y26_N2; Node "Add0~412"
            Info: Loc. = LCCOMB_X46_Y27_N14; Node "Add0~410"
            Info: Loc. = LCCOMB_X46_Y27_N8; Node "Add0~421"
            Info: Loc. = LCCOMB_X46_Y27_N12; Node "Add0~409"
            Info: Loc. = LCCOMB_X46_Y27_N10; Node "Add0~420"
            Info: Loc. = LCCOMB_X46_Y27_N12; Node "Add0~408"
            Info: Loc. = LCCOMB_X46_Y27_N14; Node "Add0~411"
            Info: Loc. = LCCOMB_X46_Y26_N26; Node "sclk~114"
            Info: Loc. = LCCOMB_X46_Y27_N22; Node "Add0~423"
            Info: Loc. = LCCOMB_X46_Y27_N16; Node "Add0~414"
        Info: 3: + IC(0.530 ns) + CELL(0.420 ns) = 12.891 ns; Loc. = LCCOMB_X47_Y27_N6; Fanout = 1; COMB Node = 'Mux1~544'
        Info: 4: + IC(0.245 ns) + CELL(0.150 ns) = 13.286 ns; Loc. = LCCOMB_X47_Y27_N4; Fanout = 1; COMB Node = 'Mux1~545'
        Info: 5: + IC(0.258 ns) + CELL(0.275 ns) = 13.819 ns; Loc. = LCCOMB_X47_Y27_N22; Fanout = 1; COMB Node = 'Mux1~548'
        Info: 6: + IC(0.245 ns) + CELL(0.150 ns) = 14.214 ns; Loc. = LCCOMB_X47_Y27_N20; Fanout = 1; COMB Node = 'Mux1~551'
        Info: 7: + IC(0.256 ns) + CELL(0.271 ns) = 14.741 ns; Loc. = LCCOMB_X47_Y27_N30; Fanout = 1; COMB Node = 'Mux1~561'
        Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 14.825 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'
        Info: Total cell delay = 13.291 ns ( 89.65 % )
        Info: Total interconnect delay = 1.534 ns ( 10.35 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.643 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.989 ns) + CELL(0.537 ns) = 2.643 ns; Loc. = LCFF_X47_Y27_N31; Fanout = 3; REG Node = 'sdo'
        Info: Total cell delay = 1.536 ns ( 58.12 % )
        Info: Total interconnect delay = 1.107 ns ( 41.88 % )
Info: tco from clock "clk" to destination pin "i2s_sclk" through register "sclk" is 8.114 ns
    Info: + Longest clock path from clock "clk" to source register is 2.652 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.998 ns) + CELL(0.537 ns) = 2.652 ns; Loc. = LCFF_X46_Y26_N15; Fanout = 3; REG Node = 'sclk'
        Info: Total cell delay = 1.536 ns ( 57.92 % )
        Info: Total interconnect delay = 1.116 ns ( 42.08 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.212 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X46_Y26_N15; Fanout = 3; REG Node = 'sclk'
        Info: 2: + IC(0.319 ns) + CELL(0.420 ns) = 0.739 ns; Loc. = LCCOMB_X46_Y26_N4; Fanout = 1; COMB Node = 'i2s_sclk~273'
        Info: 3: + IC(1.841 ns) + CELL(2.632 ns) = 5.212 ns; Loc. = PIN_K19; Fanout = 0; PIN Node = 'i2s_sclk'
        Info: Total cell delay = 3.052 ns ( 58.56 % )
        Info: Total interconnect delay = 2.160 ns ( 41.44 % )
Info: Longest tpd from source pin "start" to destination pin "i2s_sclk" is 18.019 ns
    Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_C13; Fanout = 13; PIN Node = 'start'
    Info: 2: + IC(0.000 ns) + CELL(11.081 ns) = 12.060 ns; Loc. = LCCOMB_X46_Y26_N2; Fanout = 6; COMB LOOP Node = 'Add0~412'
        Info: Loc. = LCCOMB_X46_Y26_N16; Node "Add0~425"
        Info: Loc. = LCCOMB_X46_Y27_N18; Node "Add0~416"
        Info: Loc. = LCCOMB_X46_Y27_N20; Node "Add0~419"
        Info: Loc. = LCCOMB_X46_Y27_N18; Node "Add0~417"
        Info: Loc. = LCCOMB_X46_Y26_N30; Node "Mux3~56"
        Info: Loc. = LCCOMB_X46_Y27_N20; Node "Add0~418"
        Info: Loc. = LCCOMB_X46_Y26_N0; Node "Add0~413"
        Info: Loc. = LCCOMB_X46_Y27_N24; Node "Add0~422"
        Info: Loc. = LCCOMB_X46_Y27_N16; Node "Add0~415"
        Info: Loc. = LCCOMB_X46_Y26_N2; Node "Add0~412"
        Info: Loc. = LCCOMB_X46_Y27_N14; Node "Add0~410"
        Info: Loc. = LCCOMB_X46_Y27_N8; Node "Add0~421"
        Info: Loc. = LCCOMB_X46_Y27_N12; Node "Add0~409"
        Info: Loc. = LCCOMB_X46_Y27_N10; Node "Add0~420"
        Info: Loc. = LCCOMB_X46_Y27_N12; Node "Add0~408"
        Info: Loc. = LCCOMB_X46_Y27_N14; Node "Add0~411"
        Info: Loc. = LCCOMB_X46_Y26_N26; Node "sclk~114"
        Info: Loc. = LCCOMB_X46_Y27_N22; Node "Add0~423"
        Info: Loc. = LCCOMB_X46_Y27_N16; Node "Add0~414"
    Info: 3: + IC(0.274 ns) + CELL(0.420 ns) = 12.754 ns; Loc. = LCCOMB_X46_Y26_N12; Fanout = 1; COMB Node = 'i2s_sclk~271'
    Info: 4: + IC(0.247 ns) + CELL(0.150 ns) = 13.151 ns; Loc. = LCCOMB_X46_Y26_N6; Fanout = 1; COMB Node = 'i2s_sclk~272'
    Info: 5: + IC(0.245 ns) + CELL(0.150 ns) = 13.546 ns; Loc. = LCCOMB_X46_Y26_N4; Fanout = 1; COMB Node = 'i2s_sclk~273'
    Info: 6: + IC(1.841 ns) + CELL(2.632 ns) = 18.019 ns; Loc. = PIN_K19; Fanout = 0; PIN Node = 'i2s_sclk'
    Info: Total cell delay = 15.412 ns ( 85.53 % )
    Info: Total interconnect delay = 2.607 ns ( 14.47 % )
Info: th for register "sd[13]" (data pin = "data[13]", clock pin = "clk") is 0.193 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.643 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 2; CLK Node = 'clk'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 27; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.989 ns) + CELL(0.537 ns) = 2.643 ns; Loc. = LCFF_X46_Y27_N7; Fanout = 1; REG Node = 'sd[13]'
        Info: Total cell delay = 1.536 ns ( 58.12 % )
        Info: Total interconnect delay = 1.107 ns ( 41.88 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.716 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_D13; Fanout = 1; PIN Node = 'data[13]'
        Info: 2: + IC(1.504 ns) + CELL(0.149 ns) = 2.632 ns; Loc. = LCCOMB_X46_Y27_N6; Fanout = 1; COMB Node = 'sd[13]~feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.716 ns; Loc. = LCFF_X46_Y27_N7; Fanout = 1; REG Node = 'sd[13]'
        Info: Total cell delay = 1.212 ns ( 44.62 % )
        Info: Total interconnect delay = 1.504 ns ( 55.38 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Dec 16 22:16:45 2008
    Info: Elapsed time: 00:00:02