📄 audio.tan.rpt
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Timing Analyzer report for audio
Tue Dec 16 22:16:45 2008
Version 6.0 Build 178 04/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk'
6. tsu
7. tco
8. tpd
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 12.146 ns ; start ; sdo ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 8.114 ns ; sclk ; i2s_sclk ; clk ; -- ; 0 ;
; Worst-case tpd ; N/A ; None ; 18.019 ns ; start ; i2s_sclk ; -- ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 0.193 ns ; data[13] ; sd[13] ; -- ; clk ; 0 ;
; Clock Setup: 'clk' ; N/A ; None ; 349.28 MHz ( period = 2.863 ns ) ; sdo ; sdo ; clk ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+----------+----------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C35F672C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk' ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 349.28 MHz ( period = 2.863 ns ) ; sdo ; sdo ; clk ; clk ; None ; None ; 2.649 ns ;
; N/A ; 380.08 MHz ( period = 2.631 ns ) ; sd[8] ; sdo ; clk ; clk ; None ; None ; 2.416 ns ;
; N/A ; 384.17 MHz ( period = 2.603 ns ) ; sd[19] ; sdo ; clk ; clk ; None ; None ; 2.389 ns ;
; N/A ; 388.05 MHz ( period = 2.577 ns ) ; sd[10] ; sdo ; clk ; clk ; None ; None ; 2.362 ns ;
; N/A ; 389.41 MHz ( period = 2.568 ns ) ; sd[20] ; sdo ; clk ; clk ; None ; None ; 2.353 ns ;
; N/A ; 391.85 MHz ( period = 2.552 ns ) ; sd[14] ; sdo ; clk ; clk ; None ; None ; 2.329 ns ;
; N/A ; 393.55 MHz ( period = 2.541 ns ) ; sd[13] ; sdo ; clk ; clk ; None ; None ; 2.327 ns ;
; N/A ; 401.77 MHz ( period = 2.489 ns ) ; sd[17] ; sdo ; clk ; clk ; None ; None ; 2.275 ns ;
; N/A ; 403.71 MHz ( period = 2.477 ns ) ; sd[21] ; sdo ; clk ; clk ; None ; None ; 2.263 ns ;
; N/A ; 404.69 MHz ( period = 2.471 ns ) ; sd[23] ; sdo ; clk ; clk ; None ; None ; 2.257 ns ;
; N/A ; 413.56 MHz ( period = 2.418 ns ) ; sd[15] ; sdo ; clk ; clk ; None ; None ; 2.195 ns ;
; N/A ; 416.32 MHz ( period = 2.402 ns ) ; sd[16] ; sdo ; clk ; clk ; None ; None ; 2.188 ns ;
; N/A ; 419.29 MHz ( period = 2.385 ns ) ; sd[4] ; sdo ; clk ; clk ; None ; None ; 2.171 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[22] ; sdo ; clk ; clk ; None ; None ; 2.132 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[9] ; sdo ; clk ; clk ; None ; None ; 2.124 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[12] ; sdo ; clk ; clk ; None ; None ; 2.048 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[18] ; sdo ; clk ; clk ; None ; None ; 2.049 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[5] ; sdo ; clk ; clk ; None ; None ; 1.862 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[11] ; sdo ; clk ; clk ; None ; None ; 1.838 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[7] ; sdo ; clk ; clk ; None ; None ; 1.735 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[6] ; sdo ; clk ; clk ; None ; None ; 1.727 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[3] ; sdo ; clk ; clk ; None ; None ; 1.655 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sclk ; sclk ; clk ; clk ; None ; None ; 1.621 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[2] ; sdo ; clk ; clk ; None ; None ; 1.609 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[1] ; sdo ; clk ; clk ; None ; None ; 1.459 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; sd[0] ; sdo ; clk ; clk ; None ; None ; 1.332 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; over~reg0 ; over~reg0 ; clk ; clk ; None ; None ; 0.407 ns ;
+-------+------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+
+---------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+----------+-----------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+----------+-----------+----------+
; N/A ; None ; 12.146 ns ; start ; sdo ; clk ;
; N/A ; None ; 11.712 ns ; start ; sclk ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[2] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[1] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[0] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[5] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[6] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[7] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[23] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[19] ; clk ;
; N/A ; None ; 9.972 ns ; start ; sd[9] ; clk ;
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