clock.vhd

ALTERA的语音芯片程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk,over,reset : in std_logic;
     mclk,sclk,start : out std_logic;
     data : out std_logic_vector(23 downto 0));
end;
architecture bhv of clock is
type rom is array(0 to 8) of std_logic_vector(15 downto 0);
signal reg : rom;
signal addr : integer range 0 to 8;
signal sclktemp,mclktemp,flag : std_logic;
signal vol : std_logic_vector(6 downto 0);
signal cnt0 : integer range 0 to 1;
signal cnt1 : integer range 0 to 24;
signal data_a : std_logic_vector(15 downto 0);
begin
 mclk<=mclktemp;sclk<=sclktemp;data<="00110100" & data_a;
 start<=flag when (addr<9) and (over='1') else
        '1';
 process(clk)
 begin
  if clk'event and clk='1' then
   if cnt1=24 then cnt1<=0;sclktemp<=not sclktemp;
   else cnt1<=cnt1+1;
   end if;
   if cnt0=1 then cnt0<=0;mclktemp<=not mclktemp;
   else cnt0<=cnt0+1;
   end if;
  end if;
 end process;
 process(sclktemp)
 begin
  if sclktemp'event and sclktemp='1' then
   flag<=not flag;
  end if;
 end process;
 process(reset,over)
 begin
  if reset='0' then addr<=0;
  else 
   if over'event and over='1' then
    if addr<8 then addr<=addr+1;end if;
   end if;
  end if;   
 end process;
 process(reset)
 begin
  if reset'event and reset='1' then
   if vol<"0111101" then vol<="1111111";
   else vol<=vol-"0001010";
   end if;
  end if;
 end process; 
 process(over,addr)
 begin
  if over'event and over='1' then
   reg(0)<="0000110000000000"; 	     --power down
   reg(1)<="0000111011000001"; 	     --mode select  left adjust
   reg(2)<="0000100000010101"; 	     --sound select 0000_1000_0001_0101
   reg(3)<="0001000000001100";
   reg(4)<="0000000000010111"; 		 --lin vol
   reg(5)<="0000001000010111"; 	     --rin vol
   reg(6)<="0000010001111111"; --& vol(6 downto 0);	    --lsound vol
   reg(7)<="0000011001111111"; --& vol(6 downto 0);	    --rsound vol	
   reg(8)<="0001001000000001";        --active
   data_a<=reg(addr);
  end if;
 end process;
end;