audiochip.vhd

ALTERA的语音芯片程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity audiochip is
port(clk,start : in std_logic;
     data : in std_logic_vector(23 downto 0);
     i2c_sdat,i2c_sclk,over : out std_logic);
end;
architecture bhv of audiochip is
signal sdcnt : integer range 0 to 32;
signal sd : std_logic_vector(23 downto 0);
signal sclk,sdo,clock : std_logic;
begin
 i2c_sclk<=sclk or clock;i2c_sdat<=sdo;
 process(clk,sdcnt)
 begin
  if (sdcnt>=4) and (sdcnt<=30) then clock<=not clk;
  else clock<='0';
  end if;
 end process;
 process(start,clk)
 begin
  if start='0' then sdcnt<=0;
  else
   if clk'event and clk='1' then
    if sdcnt<32 then sdcnt<=sdcnt+1;end if;
   end if;
  end if;
 end process;
 process(clk,sdcnt)
 begin
  if clk'event and clk='1' then
   case sdcnt is
    when 0 =>over<='0'; sdo<='1'; sclk<='1';
    when 1 =>sd<=data; sdo<='0';
    when 2 =>sclk<='0';
    when 3 =>sdo<=sd(23);
    when 4 =>sdo<=sd(22);
    when 5 =>sdo<=sd(21);
    when 6 =>sdo<=sd(20);
    when 7 =>sdo<=sd(19);
    when 8 =>sdo<=sd(18);
    when 9 =>sdo<=sd(17);
    when 10 =>sdo<=sd(16);
    when 11 =>sdo<='0';
    when 12 =>sdo<=sd(15);
    when 13 =>sdo<=sd(14);
    when 14 =>sdo<=sd(13);
    when 15 =>sdo<=sd(12);
    when 16 =>sdo<=sd(11);
    when 17 =>sdo<=sd(10);
    when 18 =>sdo<=sd(9);
    when 19 =>sdo<=sd(8);
    when 20 =>sdo<='0';
    when 21 =>sdo<=sd(7);
    when 22 =>sdo<=sd(6);
    when 23 =>sdo<=sd(5);
    when 24 =>sdo<=sd(4);
    when 25 =>sdo<=sd(3);
    when 26 =>sdo<=sd(2);
    when 27 =>sdo<=sd(1);
    when 28 =>sdo<=sd(0);
    when 29 =>sdo<='0';
    when 30 =>sdo<='0';sclk<='0';
    when 31 =>sclk<='1';
    when 32 =>sdo<='1';over<='1';
    when others =>sdo<='1';
   end case;
  end if;
 end process;
end;