audio.map.rpt

ALTERA的语音芯片程序

+----------------------------------+-----------------+-----------------+------------------------------+
; audio1.vhd                       ; yes             ; User VHDL File  ; G:/debug/audio/audio1.vhd    ;
+----------------------------------+-----------------+-----------------+------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 43    ;
; Total combinational functions               ; 43    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 27    ;
;     -- 3 input functions                    ; 7     ;
;     -- <=2 input functions                  ; 9     ;
;         -- Combinational cells for routing  ; 0     ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 38    ;
;     -- arithmetic mode                      ; 5     ;
; Total registers                             ; 27    ;
; I/O pins                                    ; 29    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 28    ;
; Total fan-out                               ; 227   ;
; Average fan-out                             ; 2.29  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                 ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
; |audio1                    ; 43 (43)           ; 27 (27)      ; 0           ; 0    ; 0            ; 0       ; 0         ; 29   ; 0            ; |audio1             ;
+----------------------------+-------------------+--------------+-------------+------+--------------+---------+-----------+------+--------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------+
; Logic Cells Representing Combinational Loops               ;
+--------------------------------------------------------+---+
; Logic Cell Name                                        ;   ;
+--------------------------------------------------------+---+
; Add0~0                                                 ;   ;
; Add0~2                                                 ;   ;
; Add0~3                                                 ;   ;
; Add0~4                                                 ;   ;
; Add0~5                                                 ;   ;
; Add0~1                                                 ;   ;
; Number of logic cells representing combinational loops ; 6 ;
+--------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 27    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 24    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 6 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; No         ; |audio1|scnt[5]            ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Dec 16 22:15:05 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off audio -c audio
Info: Found 2 design units, including 1 entities, in source file audiochip.vhd
    Info: Found design unit 1: audiochip-bhv
    Info: Found entity 1: audiochip
Info: Found 2 design units, including 1 entities, in source file changer.vhd
    Info: Found design unit 1: changer-bhv
    Info: Found entity 1: changer
Info: Found 2 design units, including 1 entities, in source file clock.vhd
    Info: Found design unit 1: clock-bhv
    Info: Found entity 1: clock
Info: Found 2 design units, including 1 entities, in source file fifo.vhd
    Info: Found design unit 1: myfifo-bhv
    Info: Found entity 1: myfifo
Info: Found 2 design units, including 1 entities, in source file keyvol.vhd
    Info: Found design unit 1: keyvol-bhv
    Info: Found entity 1: keyvol
Info: Found 2 design units, including 1 entities, in source file source_serial_parallel.vhd
    Info: Found design unit 1: source_serial_parallel-shift
    Info: Found entity 1: source_serial_parallel
Info: Found 2 design units, including 1 entities, in source file audio1.vhd
    Info: Found design unit 1: audio1-bhv
    Info: Found entity 1: audio1
Info: Elaborating entity "audio1" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at audio1.vhd(20): signal "scnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at audio1.vhd(23): signal "scnt" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 96 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 3 output pins
    Info: Implemented 67 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Dec 16 22:15:08 2008
    Info: Elapsed time: 00:00:04