fifo.vhd

来自「ALTERA的语音芯片程序」· VHDL 代码 · 共 40 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity myfifo is
port(wrclk,rdclk : in std_logic;
     wrreq,rdreq : in std_logic;
     datain : in std_logic_vector(15 downto 0);
     dataend : out std_logic;
     dataout : out std_logic_vector(15 downto 0));
end;
architecture bhv of myfifo is
signal cnt,cnt0 : integer range 0 to 7;
type memory is array(0 to 7) of std_logic_vector(15 downto 0);
signal data : memory;
begin
 process(wrclk,wrreq,datain)
 begin
  if wrreq='1' then 
   if wrclk'event and wrclk='1' then data(cnt)<=datain;
    if cnt=7 then cnt<=0;
    else cnt<=cnt+1;
    end if;
   end if;
  end if;
 end process;
 process(rdclk,rdreq)
 begin
  if rdreq='1' then
   if rdclk'event and rdclk='1' then
    if cnt=0 then dataend<='0';
    else dataend<='1';dataout<=data(cnt0);
     if cnt0=7 then cnt0<=0;
     else cnt0<=cnt0+1;
     end if;  
    end if;
   end if;
  end if;
 end process;
end;