sdram.ptf

ALTERA的语音芯片程序

SYSTEM sdram
{
   System_Wizard_Version = "6.00";
   System_Wizard_Build = "178";
   WIZARD_SCRIPT_ARGUMENTS 
   {
      device_family = "CYCLONEII";
      clock_freq = "50000000";
      generate_hdl = "1";
      generate_sdk = "1";
      do_build_sim = "1";
      hardcopy_compatible = "0";
      board_class = "";
      CLOCKS 
      {
         CLOCK clk
         {
            frequency = "50000000";
            source = "External";
            display_name = "clk";
            Is_Clock_Source = "0";
         }
      }
      hdl_language = "vhdl";
      device_family_id = "CYCLONEII";
      view_master_columns = "1";
      view_master_priorities = "0";
      name_column_width = "230";
      desc_column_width = "231";
      bustype_column_width = "0";
      base_column_width = "75";
      clock_column_width = "79";
      end_column_width = "75";
      view_frame_window = "maximized";
      BOARD_INFO 
      {
         altera_avalon_cfi_flash 
         {
            reference_designators = "";
         }
         altera_avalon_epcs_flash_controller 
         {
            reference_designators = "";
         }
      }
   }
   MODULE sdram_0
   {
      class = "altera_avalon_new_sdram_controller";
      class_version = "6.0";
      iss_model_name = "altera_memory";
      SLAVE s1
      {
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Maximum_Pending_Read_Transactions = "9";
            Read_Wait_States = "peripheral_controlled";
            Write_Wait_States = "peripheral_controlled";
            Is_Memory_Device = "1";
            Address_Width = "22";
            Data_Width = "32";
            Simulation_Num_Lanes = "1";
         }
         PORT_WIRING 
         {
            # These are the top level ports.
            # Avalon ports will be added during system generation.
            PORT zs_addr
            {
               direction = "output";
               width = "12";
               Is_Enabled = "0";
            }
            PORT zs_ba
            {
               direction = "output";
               width = "2";
               Is_Enabled = "0";
            }
            PORT zs_cas_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "0";
            }
            PORT zs_cke
            {
               direction = "output";
               width = "1";
               Is_Enabled = "0";
            }
            PORT zs_cs_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "0";
            }
            PORT zs_dq
            {
               direction = "inout";
               width = "32";
               Is_Enabled = "0";
            }
            PORT zs_dqm
            {
               direction = "output";
               width = "4";
               Is_Enabled = "0";
            }
            PORT zs_ras_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "0";
            }
            PORT zs_we_n
            {
               direction = "output";
               width = "1";
               Is_Enabled = "0";
            }
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Instantiate_In_System_Module = "1";
         Is_Enabled = "1";
         Default_Module_Name = "sdram";
         Disable_Simulation_Port_Wiring = "1";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            Settings_Summary = "4194304 x 32<br>
                Memory size: 16 MBytes<br>
                128 MBits
                <br>Sharing Pins Via Tristate Bridge";
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         register_data_in = "1";
         sim_model_base = "1";
         sdram_data_width = "32";
         sdram_addr_width = "12";
         sdram_row_width = "12";
         sdram_col_width = "8";
         sdram_num_chipselects = "1";
         sdram_num_banks = "4";
         refresh_period = "15.625";
         powerup_delay = "100";
         cas_latency = "3";
         t_rfc = "70";
         t_rp = "20";
         t_mrd = "3";
         t_rcd = "20";
         t_ac = "5.5";
         t_wr = "14";
         init_refresh_commands = "2";
         init_nop_delay = "0";
         shared_data = "1";
         starvation_indicator = "0";
         tristate_bridge_slave = "";
         is_initialized = "1";
         sdram_bank_width = "2";
      }
      SIMULATION 
      {
         Fix_Me_Up = "";
         DISPLAY 
         {
            # These signals are "of interest" and are added to the waveform window, etc.
            # The name of the section (e.g. "a2" or "f") doesn't "mean" anything, except
            # that the signals will be displayed in the waveform window in-order, as
            # sorted by these otherwise-meaningless names.
            SIGNAL a
            {
               name = "az_addr";
               radix = "hexadecimal";
            }
            SIGNAL b
            {
               name = "az_be_n";
               radix = "hexadecimal";
            }
            SIGNAL c
            {
               name = "az_cs";
            }
            SIGNAL d
            {
               name = "az_data";
               radix = "hexadecimal";
            }
            SIGNAL e
            {
               name = "az_rd_n";
            }
            SIGNAL f
            {
               name = "az_wr_n";
            }
            SIGNAL g
            {
               name = "clk";
            }
            SIGNAL h
            {
               name = "za_data";
               radix = "hexadecimal";
            }
            SIGNAL i
            {
               name = "za_valid";
            }
            SIGNAL j
            {
               name = "za_waitrequest";
            }
            SIGNAL k
            {
               name = "za_cannotrefresh";
               suppress = "1";
            }
            SIGNAL l
            {
               name = "CODE";
               radix = "ascii";
            }
            SIGNAL m
            {
               name = "zs_addr";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL n
            {
               name = "zs_ba";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL o
            {
               name = "zs_cs_n";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL p
            {
               name = "zs_ras_n";
               suppress = "1";
            }
            SIGNAL q
            {
               name = "zs_cas_n";
               suppress = "1";
            }
            SIGNAL r
            {
               name = "zs_we_n";
               suppress = "1";
            }
            SIGNAL s
            {
               name = "zs_dq";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL t
            {
               name = "zs_dqm";
               radix = "hexadecimal";
               suppress = "1";
            }
            SIGNAL u
            {
               name = "zt_addr";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL v
            {
               name = "zt_ba";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL w
            {
               name = "zt_oe";
               suppress = "0";
            }
            SIGNAL x
            {
               name = "zt_cke";
               suppress = "0";
            }
            SIGNAL y
            {
               name = "zt_chipselect";
               suppress = "0";
            }
            SIGNAL z0
            {
               name = "zt_lock_n";
               suppress = "0";
            }
            SIGNAL z1
            {
               name = "zt_ras_n";
               suppress = "0";
            }
            SIGNAL z2
            {
               name = "zt_cas_n";
               suppress = "0";
            }
            SIGNAL z3
            {
               name = "zt_we_n";
               suppress = "0";
            }
            SIGNAL z4
            {
               name = "zt_cs_n";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL z5
            {
               name = "zt_dqm";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL z6
            {
               name = "zt_data";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL z7
            {
               name = "tz_data";
               radix = "hexadecimal";
               suppress = "0";
            }
            SIGNAL z8
            {
               name = "tz_waitrequest";
               suppress = "0";
            }
         }
      }
   }
   MODULE cfi_flash_0
   {
      class = "altera_avalon_cfi_flash";
      class_version = "6.0";
      iss_model_name = "altera_avalon_flash";
      HDL_INFO 
      {
      }
      SLAVE s1
      {
         PORT_WIRING 
         {
            PORT data
            {
               width = "8";
               is_shared = "1";
               direction = "inout";
               type = "data";
            }
            PORT address
            {
               width = "23";
               is_shared = "1";
               direction = "input";
               type = "address";
            }
            PORT read_n
            {
               width = "1";
               is_shared = "1";
               direction = "input";
               type = "read_n";
            }
            PORT write_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "write_n";
            }
            PORT select_n
            {
               width = "1";
               is_shared = "0";
               direction = "input";
               type = "chipselect_n";
            }
         }
         WIZARD_SCRIPT_ARGUMENTS 
         {
            class = "altera_avalon_cfi_flash";
            Supports_Flash_File_System = "1";
            flash_reference_designator = "";
         }
         SYSTEM_BUILDER_INFO 
         {
            Bus_Type = "avalon_tristate";
            Is_Nonvolatile_Storage = "1";
            Is_Memory_Device = "1";
            Address_Alignment = "dynamic";
            Has_IRQ = "0";
            Base_Address = "--unknown--";
            Data_Width = "8";
            Address_Width = "23";
            Simulation_Num_Lanes = "1";
            Convert_Xs_To_0 = "1";
            Write_Wait_States = "160ns";
            Read_Wait_States = "160ns";
            Setup_Time = "40ns";
            Hold_Time = "40ns";
            Address_Span = "8388608";
         }
      }
      SYSTEM_BUILDER_INFO 
      {
         Make_Memory_Model = "1";
         Is_Enabled = "1";
         Instantiate_In_System_Module = "0";
         Top_Level_Ports_Are_Enumerated = "1";
         Clock_Source = "clk";
         View 
         {
            MESSAGES 
            {
            }
            Is_Collapsed = "1";
         }
      }
      WIZARD_SCRIPT_ARGUMENTS 
      {
         Setup_Value = "40";
         Wait_Value = "160";
         Hold_Value = "40";
         Timing_Units = "ns";
         Unit_Multiplier = "1";
         Size = "8388608";
      }
   }
}