source_serial_parallel.vhd

来自「ALTERA的语音芯片程序」· VHDL 代码 · 共 35 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY source_serial_parallel IS 
PORT ( reset,clk : IN STD_LOGIC;
             din:  IN STD_LOGIC;
	        done: out std_logic;
           dout: OUT STD_LOGIC_vector(3 downto 0));
END source_serial_parallel;

ARCHITECTURE shift OF source_serial_parallel IS
  SIGNAL  data: std_logic_vector(3 downto 0);
  signal  bitcount:std_logic_vector(1 downto 0);
  signal  doneR: std_logic;
BEGIN
  process(clk,reset)
  begin 
  if reset='0' then data<="0000";
  elsif clk'event and clk='1' then
         if bitcount="11" then bitcount<="00";
         else    bitcount<=bitcount+'1';
         end if;
         data(3 downto 0)<=data(2 downto 0)&din;
   end if;
end process;
  process(clk,reset)
  begin
  if reset='0' then doneR<='0';
  elsif bitcount="11" then doneR<='1';
  else doneR<='0';
  end if;
  end process;
  done<=doneR;
  dout<=data;
END shift;