keyvol.vhd

ALTERA的语音芯片程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity keyvol is
port(key,clk : in std_logic;
     keyon : out std_logic);
end;
architecture bhv of keyvol is
signal flag : std_logic;
signal cnt : integer range 0 to 31;
begin
 flag<='0' when (cnt=31) and (key='0') else
       '1';
 process(clk,flag)
 begin
  if flag='0' then cnt<=0;
  else
   if clk'event and clk='1' then
    if cnt<31 then cnt<=cnt+1;end if;
   end if;
  end if;
 end process;
 process(clk,cnt)
 begin
  if clk'event and clk='1' then
   if (cnt>0) and (cnt<5) then keyon<='0';
   else keyon<='1';
   end if;
  end if;
 end process;
end;