hal_msp430f1611.h

zigbee中心节点源代码

#ifndef HAL_MSP430F1611_H
#define HAL_MSP430F1611_H

// Global macros

#define ENABLE_GLOBAL_INT()     _EINT()
#define DISABLE_GLOBAL_INT()    _DINT()

// MSP430 I/O PORTS

// Port 1
#define FIFO           2  // P2.2 - Input: FIFO from CC2420 
#define FIFO_P         3  // P2.3 - Input: FIFOP from CC2420 
#define CCA            4  // P2.4 - Input:  CCA from CC2420 
#define SFD            6  // P2.6 - Input:  SFD from CC2420 
#define VREG_EN        0 // P2.0 - Output: VREG_EN to CC2420 
#define RESET_N        1  // P2.1 - Output: RESET_N to CC2420 

// Port 2
#define DCO            5  // P2.5 - Input:  DCO from VCC

// Port 3

// Port 4

// Port 5
#define CSN            0  // P5.0 - Output: SPI Chip Select (CS_N)
#define MOSI           1  // P5.1 - Output: SPI Master out - slave in (MOSI)
#define MISO           2  // P5.2 - Input:  SPI Master in - slave out (MISO)
#define SCK            3  // P5.3 - Output: SPI Serial Clock (SCLK)

// Port 6

#define PORT_INIT()\
        do {\
                WDTCTL = WDTPW + WDTHOLD;\
		P2DIR = 0x03;\
		P1DIR = 0x0f;\
                P3DIR = 0x00;\
                P4DIR = 0x00;\
                P6DIR = 0x00;\
	} while (0)

// SPI interface

#define SPI_ENABLE()    ( P5OUT &= ~BM(CSN) ) 
#define SPI_DISABLE()	( P5OUT |=  BM(CSN) ) 
#define SPI_INIT()  halSpiInit()

// CC2420 pin access

// CC2420 interface pin status
#define FIFO_IS_1       (!!(P2IN & BM(FIFO)))
#define CCA_IS_1        (!!(P2IN & BM(CCA) ))
#define RESET_IS_1      (!!(P2IN & BM(RESET_N)))
#define VREG_IS_1       (!!(P2IN & BM(VREG_EN)))
#define FIFOP_IS_1      (!!(P2IN & BM(FIFO_P)))
#define SFD_IS_1        (!!(P2IN & BM(SFD)))

// CC2420 reset pin
#define SET_RESET_INACTIVE()    ( P2OUT |=  BM(RESET_N) )    
#define SET_RESET_ACTIVE()      ( P2OUT &= ~BM(RESET_N) )

// CC2420 voltage regulator enable pin
#define SET_VREG_ACTIVE()       ( P2OUT |=  BM(VREG_EN) )
#define SET_VREG_INACTIVE()     ( P2OUT &= ~BM(VREG_EN) )

//External interface interrupts

// FIFOP on external interrupt 0
#define ENABLE_FIFOP_INT()          do { P2IE |= BM(FIFO_P); } while (0)
#define DISABLE_FIFOP_INT()         do { P2IE &= ~BM(FIFO_P); } while (0)
#define CLEAR_FIFOP_INT()           do { P2IFG &= ~BM(FIFO_P); } while (0)
#define FIFOP_INT_INIT()            do { P2IES &= ~BM(FIFO_P); CLEAR_FIFOP_INT(); } while (0)

// SFD interrupt 
#define ENABLE_SFD_CAPTURE_INT()    do { P2IE |= BM(SFD); } while (0)
#define DISABLE_SFD_CAPTURE_INT()   do { P2IE &= ~BM(SFD); } while (0)
#define CLEAR_SFD_CAPTURE_INT()     do { P2IFG &= ~BM(SFD); } while (0)
#define SFD_INT_INIT()            do { P2IES &= ~BM(SFD); CLEAR_SFD_CAPTURE_INT(); } while (0)

#endif