dw8051_op_decoder.v

来自「DW8051 Verilog VHDL 源码和文档」· Verilog 代码 · 共 1,245 行 · 第 1/4 页

                                chg_flags  <= 1'b1;
                              end
                   endcase
                 end
        4'b1010: begin
                   case (op[3:0])
                     4'b0000: begin		    // ORL C, ~(direct_bit)
                                itype      <=  6;
                                src        <=  7;
                                src_cycle  <=  1;
                                alu_op     <= `alu_op_orlcbn;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// MOV C, direct_bit
                                itype      <=  6;
                                src        <=  7;
                                src_cycle  <=  1;
                                alu_op     <= `alu_op_movcb;
                              end
                     4'b0011: begin			// INC DPTR
                                itype      <=  12;
                                last_cycle <=  2;
                                dest       <=  14;
                              end
                     4'b0100: begin			// MUL AB
                                itype      <=  28;
                                last_cycle <=  4;
                                alu_op     <= `alu_op_mul;
                              end
                     4'b0101: begin			// reserved (= NOP)
                                itype      <=  0;
                                last_cycle <=  0;
                              end
                     4'b0110,				// MOV @R0, direct
		     4'b0111: begin			// MOV @R1, direct
                                itype      <=  5;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  4;
                              end
                     default: begin			// MOV [R0..R7], direct
                                itype      <=  5;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  2;
                              end
                   endcase
                 end
        4'b1011: begin
                   case (op[3:0])
                     4'b0000: begin		     // ANL C, ~(direct_bit)
                                itype      <=  6;
                                src        <=  7;
                                src_cycle  <=  1;
                                alu_op     <= `alu_op_anlcbn;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// CPL direct_bit
                                itype      <=  5;
                                src        <=  7;
                                src_cycle  <=  1;
                                dest       <=  7;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_cplb;
                              end
                     4'b0011: begin			// CPL C
                                itype      <=  1;
                                last_cycle <=  0;
                                alu_op     <= `alu_op_cplc;
                                chg_flags  <= 1'b1;
                              end
                     4'b0100: begin			// CJNE A, #imm8, rel
                                itype      <=  22;
                                last_cycle <=  3;
                                src        <=  1;
                              end
                     4'b0101: begin			// CJNE A, direct, rel
                                itype      <=  22;
                                last_cycle <=  3;
                                src        <=  1;
                              end
                     4'b0110,				// CJNE @R0,#imm8,rel
		     4'b0111: begin			// CJNE @R1,#imm8,rel
                                itype      <=  22;
                                last_cycle <=  3;
                                src        <=  4;
                              end
                     default: begin		// CJNE [R0..R7], #data, rel
                                itype      <=  22;
                                last_cycle <=  3;
                                src        <=  2;
                              end
                   endcase
                 end
        4'b1100: begin
                   case (op[3:0])
                     4'b0000: begin			// PUSH direct
                                itype      <=  7;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  12;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// CLR direct_bit
                                itype      <=  5;
                                src        <=  7;
                                src_cycle  <=  1;
                                dest       <=  7;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_clrb;
                              end
                     4'b0011: begin			// CLR C
                                itype      <=  1;
                                last_cycle <=  0;
                                alu_op     <= `alu_op_clrc;
                                chg_flags  <= 1'b1;
                              end
                     4'b0100: begin			// SWAP A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_swap;
                              end
                     4'b0101: begin			// XCH A, direct
                                itype      <=  5;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  9;
                              end
                     4'b0110,				// XCH A, @R0
		     4'b0111: begin			// XCH A, @R1
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  10;
                              end
                     default: begin			// XCH A,[R0..R7]
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  9;
                              end
                   endcase
                 end
        4'b1101: begin
                   case (op[3:0])
                     4'b0000: begin			// POP direct
                                itype      <=  7;
                                src        <=  12;
                                src_cycle  <=  1;
                                dest       <=  3;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010: begin			// SETB direct_bit
                                itype      <=  5;
                                src        <=  7;
                                src_cycle  <=  1;
                                dest       <=  7;
                                rmw        <= 1'b1;
                                alu_op     <= `alu_op_setbb;
                              end
                     4'b0011: begin			// SETB C
                                itype      <=  1;
                                last_cycle <=  0;
                                alu_op     <= `alu_op_setbc;
                                chg_flags  <= 1'b1;
                              end
                     4'b0100: begin			// DA A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_da;
                                chg_flags  <= 1'b1;
                              end
                     4'b0101: begin			//DJNZ direct,rel
                                itype      <=  26;
                                last_cycle <=  3;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  3;
                                alu_op     <= `alu_op_dec;
                                rmw        <= 1'b1;
                              end
                     4'b0110,				// XCHD A, @R0
		     4'b0111: begin			// XCHD A, @R1
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  11;
                              end
                     default: begin		  // DJNZ [R0..R7], rel
                                itype      <=  13;
                                last_cycle <=  2;
                                src        <=  2;
                                dest       <=  2;
                                alu_op     <= `alu_op_dec;
                              end
                   endcase
                 end
        4'b1110: begin
                   case (op[3:0])
                     4'b0000: begin			// MOVX A,@DPTR
                                itype      <=  8;
                                src        <=  15;
                                dest       <=  5;
                              end
                     4'b0001: begin			// AJMP addr11
                                itype      <=  15;
                                last_cycle <=  2;
                              end
                     4'b0010,				// MOVX A,@R0
		     4'b0011: begin			// MOVX A,@R1
                                itype      <=  8;
                                src        <=  6;
                                dest       <=  5;
                              end
                     4'b0100: begin			// CLR A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_clr;
                              end
                     4'b0101: begin			// MOV A,direct
                                itype      <=  5;
                                src        <=  3;
                                src_cycle  <=  1;
                                dest       <=  1;
                              end
                     4'b0110,				// MOV A, @R0
		     4'b0111: begin			// MOV A, @R1
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  4;
                                dest       <=  1;
                              end
                     default: begin			// MOV A,[R0..R7]
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  2;
                                dest       <=  1;
                              end
                   endcase
                 end
        4'b1111: begin
                   case (op[3:0])
                     4'b0000: begin			// MOVX @DPTR,A
                                itype      <=  8;
                                dest       <=  15;
                              end
                     4'b0001: begin			// ACALL addr11
                                itype      <=  14;
                                last_cycle <=  2;
                              end
                     4'b0010,				// MOVX @R0, A
		     4'b0011: begin			// MOVX @R1, A
                                itype      <=  8;
                                src        <=  8;
                                dest       <=  6;
                              end
                     4'b0100: begin			// CPL A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  1;
                                alu_op     <= `alu_op_cpl;
                              end
                     4'b0101: begin			// MOV direct, A
                                itype      <=  5;
                                src        <=  1;
                                dest       <=  3;
                              end
                     4'b0110,				// MOV @R0,A
		     4'b0111: begin			// MOV @R1,A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  4;
                              end
                     default: begin			// MOV [R0..R7],A
                                itype      <=  1;
                                last_cycle <=  0;
                                src        <=  1;
                                dest       <=  2;
                              end
                   endcase
                 end
        default: begin end
      endcase
    end 
 end 


endmodule