ch8_matrix.qsf

用fpga+usb显现的4通道800K的数据采集方案。

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		CH8_Matrix_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name DEVICE EP2C70F896C8
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name TOP_LEVEL_ENTITY CH8_Matrix
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:16:27  AUGUST 24, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION 7.0
set_global_assignment -name ENABLE_DEVICE_WIDE_RESET ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name OUTPUT_PIN_LOAD 8 -section_id "3.3-V LVTTL"
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_location_assignment PIN_K29 -to AD_in[13]
set_location_assignment PIN_K28 -to AD_in[12]
set_location_assignment PIN_J26 -to AD_in[11]
set_location_assignment PIN_J30 -to AD_in[10]
set_location_assignment PIN_J29 -to AD_in[9]
set_location_assignment PIN_H27 -to AD_in[8]
set_location_assignment PIN_H30 -to AD_in[7]
set_location_assignment PIN_H28 -to AD_in[6]
set_location_assignment PIN_H29 -to AD_in[5]
set_location_assignment PIN_G27 -to AD_in[4]
set_location_assignment PIN_G30 -to AD_in[3]
set_location_assignment PIN_G29 -to AD_in[2]
set_location_assignment PIN_G28 -to AD_in[1]
set_location_assignment PIN_F30 -to AD_in[0]
set_location_assignment PIN_A17 -to D_sin[0]
set_location_assignment PIN_B17 -to D_sin[1]
set_location_assignment PIN_C17 -to D_sin[2]
set_location_assignment PIN_B18 -to D_sin[3]
set_location_assignment PIN_C18 -to D_sin[4]
set_location_assignment PIN_A19 -to D_sin[5]
set_location_assignment PIN_B19 -to D_sin[6]
set_location_assignment PIN_A20 -to D_sin[7]
set_location_assignment PIN_D10 -to PS10
set_location_assignment PIN_B9 -to TB_DDS
set_location_assignment PIN_C16 -to TP_232
set_location_assignment PIN_C10 -to TP_DDS
set_location_assignment PIN_A8 -to Update1
set_location_assignment PIN_T2 -to CLK_40M
set_location_assignment PIN_C28 -to SLWR
set_global_assignment -name SMART_RECOMPILE ON
set_location_assignment PIN_A25 -to D_sin[8]
set_location_assignment PIN_B25 -to D_sin[9]
set_location_assignment PIN_A26 -to D_sin[10]
set_location_assignment PIN_B26 -to D_sin[11]
set_location_assignment PIN_C26 -to D_sin[12]
set_location_assignment PIN_C27 -to D_sin[13]
set_location_assignment PIN_B27 -to D_sin[14]
set_location_assignment PIN_A28 -to D_sin[15]
set_location_assignment PIN_AD6 -to AD_CLK
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_location_assignment PIN_A7 -to led3
set_location_assignment PIN_A3 -to led1
set_location_assignment PIN_B28 -to RDY0
set_location_assignment PIN_C4 -to led2
set_global_assignment -name VECTOR_WAVEFORM_FILE CH8_Matrix.vwf
set_global_assignment -name BDF_FILE CH8_Matrix.bdf
set_global_assignment -name VERILOG_FILE my_DFF.v
set_global_assignment -name VERILOG_FILE update_pulse.v
set_global_assignment -name VERILOG_FILE lpm_dff0.v
set_global_assignment -name VERILOG_FILE HM_address.v
set_global_assignment -name VERILOG_FILE HM_Tab.v
set_global_assignment -name VERILOG_FILE div5.v
set_global_assignment -name VERILOG_FILE DDS_straight.v
set_global_assignment -name VERILOG_FILE gating_pulse.v
set_global_assignment -name VERILOG_FILE bit_cut.v
set_global_assignment -name VERILOG_FILE AD_2Compl.v
set_global_assignment -name VERILOG_FILE div_mult.v
set_global_assignment -name VERILOG_FILE widen_bit.v
set_global_assignment -name VERILOG_FILE DDS_straight_new.v
set_global_assignment -name VERILOG_FILE wait2s.v
set_global_assignment -name VERILOG_FILE counter.v
set_location_assignment PIN_F29 -to PDWN8
set_location_assignment PIN_B21 -to PC0