ch8_matrix.tan.qmsg

用fpga+usb显现的4通道800K的数据采集方案。

{ "Info" "ITDB_FULL_TPD_RESULT" "PC0 led1 12.329 ns Longest " "Info: Longest tpd from source pin \"PC0\" to destination pin \"led1\" is 12.329 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns PC0 1 PIN PIN_B21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_B21; Fanout = 2; PIN Node = 'PC0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { PC0 } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -576 120 288 -560 "PC0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.879 ns) + CELL(3.506 ns) 12.329 ns led1 2 PIN PIN_A3 0 " "Info: 2: + IC(7.879 ns) + CELL(3.506 ns) = 12.329 ns; Loc. = PIN_A3; Fanout = 0; PIN Node = 'led1'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "11.385 ns" { PC0 led1 } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -696 328 504 -680 "led1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.450 ns ( 36.09 % ) " "Info: Total cell delay = 4.450 ns ( 36.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.879 ns ( 63.91 % ) " "Info: Total interconnect delay = 7.879 ns ( 63.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "12.329 ns" { PC0 led1 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "12.329 ns" { PC0 PC0~combout led1 } { 0.000ns 0.000ns 7.879ns } { 0.000ns 0.944ns 3.506ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "my_DFF:inst10\|Q PC0 CLK_40M 13.321 ns register " "Info: th for register \"my_DFF:inst10\|Q\" (data pin = \"PC0\", clock pin = \"CLK_40M\") is 13.321 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M destination 21.582 ns + Longest register " "Info: + Longest clock path from clock \"CLK_40M\" to destination register is 21.582 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK_40M 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'CLK_40M'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_40M } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.135 ns) + CELL(0.000 ns) 1.235 ns CLK_40M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK_40M~clkctrl'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.135 ns" { CLK_40M CLK_40M~clkctrl } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.431 ns) + CELL(0.970 ns) 3.636 ns div_mult:inst8\|counter\[8\] 3 REG LCFF_X50_Y1_N19 2 " "Info: 3: + IC(1.431 ns) + CELL(0.970 ns) = 3.636 ns; Loc. = LCFF_X50_Y1_N19; Fanout = 2; REG Node = 'div_mult:inst8\|counter\[8\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.401 ns" { CLK_40M~clkctrl div_mult:inst8|counter[8] } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.000 ns) 4.645 ns div_mult:inst8\|counter\[8\]~clkctrl 4 COMB CLKCTRL_G13 9 " "Info: 4: + IC(1.009 ns) + CELL(0.000 ns) = 4.645 ns; Loc. = CLKCTRL_G13; Fanout = 9; COMB Node = 'div_mult:inst8\|counter\[8\]~clkctrl'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/prog