ch8_matrix.tan.qmsg

用fpga+usb显现的4通道800K的数据采集方案。

{ "Info" "ITDB_TSU_RESULT" "gating_pulse:inst\|counter_small_AD\[4\] flagb CLK_40M 4.913 ns register " "Info: tsu for register \"gating_pulse:inst\|counter_small_AD\[4\]\" (data pin = \"flagb\", clock pin = \"CLK_40M\") is 4.913 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.691 ns + Longest pin register " "Info: + Longest pin to register delay is 11.691 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.904 ns) 0.904 ns flagb 1 PIN PIN_G13 5 " "Info: 1: + IC(0.000 ns) + CELL(0.904 ns) = 0.904 ns; Loc. = PIN_G13; Fanout = 5; PIN Node = 'flagb'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { flagb } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -464 496 664 -448 "flagb" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(8.282 ns) + CELL(0.624 ns) 9.810 ns gating_pulse:inst\|counter_small_AD\[4\]~481 2 COMB LCCOMB_X68_Y30_N28 5 " "Info: 2: + IC(8.282 ns) + CELL(0.624 ns) = 9.810 ns; Loc. = LCCOMB_X68_Y30_N28; Fanout = 5; COMB Node = 'gating_pulse:inst\|counter_small_AD\[4\]~481'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.906 ns" { flagb gating_pulse:inst|counter_small_AD[4]~481 } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.026 ns) + CELL(0.855 ns) 11.691 ns gating_pulse:inst\|counter_small_AD\[4\] 3 REG LCFF_X67_Y29_N9 3 " "Info: 3: + IC(1.026 ns) + CELL(0.855 ns) = 11.691 ns; Loc. = LCFF_X67_Y29_N9; Fanout = 3; REG Node = 'gating_pulse:inst\|counter_small_AD\[4\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.881 ns" { gating_pulse:inst|counter_small_AD[4]~481 gating_pulse:inst|counter_small_AD[4] } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.383 ns ( 20.38 % ) " "Info: Total cell delay = 2.383 ns ( 20.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.308 ns ( 79.62 % ) " "Info: Total interconnect delay = 9.308 ns ( 79.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "11.691 ns" { flagb gating_pulse:inst|counter_small_AD[4]~481 gating_pulse:inst|counter_small_AD[4] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "11.691 ns" { flagb flagb~combout gating_pulse:inst|counter_small_AD[4]~481 gating_pulse:inst|counter_small_AD[4] } { 0.000ns 0.000ns 8.282ns 1.026ns } { 0.000ns 0.904ns 0.624ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 90 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M destination 6.738 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_40M\" to destination register is 6.738 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK_40M 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'CLK_40M'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_40M } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.135 ns) + CELL(0.000 ns) 1.235 ns CLK_40M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK_40M~clkctrl'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.135 ns" { CLK_40M CLK_40M~clkctrl } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.431 ns) + CELL(0.970 ns) 3.636 ns div_mult:inst8\|counter\[0\] 3 REG LCFF_X50_Y1_N25 4 " "Info: 3: + IC(1.431 ns) + CELL(0.970 ns) = 3.636 ns; Loc. = LCFF_X50_Y1_N25; Fanout = 4; REG Node = 'div_mult:inst8\|counter\[0\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.401 ns" { CLK_40M~clkctrl div_mult:inst8|counter[0] } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.000 ns) 4.645 ns div_mult:inst8\|counter\[0\]~clkctrl 4 COMB CLKCTRL_G12 40 " "Info: 4: + IC(1.009 ns) + CELL(0.000 ns) = 4.645 ns; Loc. = CLKCTRL_G12; Fanout = 40; COMB Node = 'div_mult:inst8\|counter\[0\]~clkctrl'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.427 ns) + CELL(0.666 ns) 6.738 ns gating_pulse:inst\|counter_small_AD\[4\] 5 REG LCFF_X67_Y29_N9 3 " "Info: 5: + IC(1.427 ns) + CELL(0.666 ns) = 6.738 ns; Loc. = LCFF_X67_Y29_N9; Fanout = 3; REG Node = 'gating_pulse:inst\|counter_small_AD\[4\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.093 ns" { div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_AD[4] } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 40.61 % ) " "Info: Total cell delay = 2.736 ns ( 40.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.002 ns ( 59.39 % ) " "Info: Total interconnect delay = 4.002 ns ( 59.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.738 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_AD[4] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "6.738 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_AD[4] } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.427ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "11.691 ns" { flagb gating_pulse:inst|counter_small_AD[4]~481 gating_pulse:inst|counter_small_AD[4] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "11.691 ns" { flagb flagb~combout gating_pulse:inst|counter_small_AD[4]~481 gating_pulse:inst|counter_small_AD[4] } { 0.000ns 0.000ns 8.282ns 1.026ns } { 0.000ns 0.904ns 0.624ns 0.855ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.738 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_AD[4] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "6.738 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_AD[4] } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.427ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK_40M D_sin\[2\] lpm_dff0:inst2\|lpm_ff:lpm_ff_component\|dffs\[2\] 20.153 ns register " "Info: tco from clock \"CLK_40M\" to destination pin \"D_sin\[2\]\" through register \"lpm_dff0:inst2\|lpm_ff:lpm_ff_component\|dffs\[2\]\" is 20.153 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M source 11.394 ns + Longest register " "Info: + Longest clock path from clock \"CLK_40M\" to source register is 11.394 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK_40M 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'CLK_40M'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_40M } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.135 ns) + CELL(0.000 ns) 1.235 ns CLK_40M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK_40M~clkctrl'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.135 ns" { CLK_40M CLK_40M~clkctrl } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.431 ns) + CELL(0.970 ns) 3.636 ns div_mult:inst8\|counter\[0\] 3 REG LCFF_X50_Y1_N25 4 " "Info: 3: + IC(1.431 ns) + CELL(0.970 ns) = 3.636 ns; Loc. = LCFF_X50_Y1_N25; Fanout = 4; REG Node = 'div_mult:inst8\|counter\[0\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.401 ns" { CLK_40M~clkctrl div_mult:inst8|counter[0] } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.000 ns) 4.645 ns div_mult:inst8\|counter\[0\]~clkctrl 4 COMB CLKCTRL_G12 40 " "Info: 4: + IC(1.009 ns) + CELL(0.000 ns) = 4.645 ns; Loc. = CLKCTRL_G12; Fanout = 40; COMB Node = 'div_mult:inst8\|counter\[0\]~clkctrl'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.970 ns) 7.038 ns gating_pulse:inst\|Get_CLK 5 REG LCFF_X67_Y30_N19 1 " "Info: 5: + IC(1.423 ns) + CELL(0.970 ns) = 7.038 ns; Loc. = LCFF_X67_Y30_N19; Fanout = 1; REG Node = 'gating_pulse:inst\|Get_CLK'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|Get_CLK } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.219 ns) + CELL(0.000 ns) 9.257 ns gating_pulse:inst\|Get_CLK~clkctrl 6 COMB CLKCTRL_G5 14 " "Info: 6: + IC(2.219 ns) + CELL(0.000 ns) = 9.257 ns; Loc. = CLKCTRL_G5; Fanout = 14; COMB Node = 'gating_pulse:inst\|Get_CLK~clkctrl'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.219 ns" { gating_pulse:inst|Get_CLK gating_pulse:inst|Get_CLK~clkctrl } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.471 ns) + CELL(0.666 ns) 11.394 ns lpm_dff0:inst2\|lpm_ff:lpm_ff_component\|dffs\[2\] 7 REG LCFF_X93_Y44_N7 1 " "Info: 7: + IC(1.471 ns) + CELL(0.666 ns) = 11.394 ns; Loc. = LCFF_X93_Y44_N7; Fanout = 1; REG Node = 'lpm_dff0:inst2\|lpm_ff:lpm_ff_component\|dffs\[2\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.137 ns" { gating_pulse:inst|Get_CLK~clkctrl lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "d:/program files/quartusii/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.706 ns ( 32.53 % ) " "Info: Total cell delay = 3.706 ns ( 32.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.688 ns ( 67.47 % ) " "Info: Total interconnect delay = 7.688 ns ( 67.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "11.394 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|Get_CLK gating_pulse:inst|Get_CLK~clkctrl lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "11.394 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|Get_CLK gating_pulse:inst|Get_CLK~clkctrl lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.423ns 2.219ns 1.471ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "lpm_ff.tdf" "" { Text "d:/program files/quartusii/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.455 ns + Longest register pin " "Info: + Longest register to pin delay is 8.455 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_dff0:inst2\|lpm_ff:lpm_ff_component\|dffs\[2\] 1 REG LCFF_X93_Y44_N7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X93_Y44_N7; Fanout = 1; REG Node = 'lpm_dff0:inst2\|lpm_ff:lpm_ff_component\|dffs\[2\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "lpm_ff.tdf" "" { Text "d:/program files/quartusii/quartus/libraries/megafunctions/lpm_ff.tdf" 62 7 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.989 ns) + CELL(3.466 ns) 8.455 ns D_sin\[2\] 2 PIN PIN_C17 0 " "Info: 2: + IC(4.989 ns) + CELL(3.466 ns) = 8.455 ns; Loc. = PIN_C17; Fanout = 0; PIN Node = 'D_sin\[2\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.455 ns" { lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] D_sin[2] } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { 24 1312 1488 40 "D_sin\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.466 ns ( 40.99 % ) " "Info: Total cell delay = 3.466 ns ( 40.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.989 ns ( 59.01 % ) " "Info: Total interconnect delay = 4.989 ns ( 59.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.455 ns" { lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] D_sin[2] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.455 ns" { lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] D_sin[2] } { 0.000ns 4.989ns } { 0.000ns 3.466ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "11.394 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|Get_CLK gating_pulse:inst|Get_CLK~clkctrl lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "11.394 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|Get_CLK gating_pulse:inst|Get_CLK~clkctrl lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.423ns 2.219ns 1.471ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.455 ns" { lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] D_sin[2] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.455 ns" { lpm_dff0:inst2|lpm_ff:lpm_ff_component|dffs[2] D_sin[2] } { 0.000ns 4.989ns } { 0.000ns 3.466ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}