📄 ch8_matrix.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "11 " "Warning: Found 11 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "gating_pulse:inst\|Get_CLK " "Info: Detected ripple clock \"gating_pulse:inst\|Get_CLK\" as buffer" { } { { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 3 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "gating_pulse:inst\|Get_CLK" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_mult:inst8\|counter\[8\] " "Info: Detected ripple clock \"div_mult:inst8\|counter\[8\]\" as buffer" { } { { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div_mult:inst8\|counter\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_mult:inst16\|counter\[8\] " "Info: Detected ripple clock \"div_mult:inst16\|counter\[8\]\" as buffer" { } { { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div_mult:inst16\|counter\[8\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_mult:inst23\|counter\[1\] " "Info: Detected ripple clock \"div_mult:inst23\|counter\[1\]\" as buffer" { } { { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div_mult:inst23\|counter\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div5:inst20\|state\[0\] " "Info: Detected ripple clock \"div5:inst20\|state\[0\]\" as buffer" { } { { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 8 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div5:inst20\|state\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div5:inst20\|clk1 " "Info: Detected ripple clock \"div5:inst20\|clk1\" as buffer" { } { { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 7 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div5:inst20\|clk1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "div5:inst20\|clk_out " "Info: Detected gated clock \"div5:inst20\|clk_out\" as buffer" { } { { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 4 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div5:inst20\|clk_out" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div5:inst19\|state\[0\] " "Info: Detected ripple clock \"div5:inst19\|state\[0\]\" as buffer" { } { { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 8 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div5:inst19\|state\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div5:inst19\|clk1 " "Info: Detected ripple clock \"div5:inst19\|clk1\" as buffer" { } { { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 7 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div5:inst19\|clk1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "div5:inst19\|clk_out " "Info: Detected gated clock \"div5:inst19\|clk_out\" as buffer" { } { { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 4 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div5:inst19\|clk_out" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_mult:inst8\|counter\[0\] " "Info: Detected ripple clock \"div_mult:inst8\|counter\[0\]\" as buffer" { } { { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "div_mult:inst8\|counter\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_40M register my_DFF:inst13\|Q register gating_pulse:inst\|counter_small_Get\[3\] 26.64 MHz 37.54 ns Internal " "Info: Clock \"CLK_40M\" has Internal fmax of 26.64 MHz between source register \"my_DFF:inst13\|Q\" and destination register \"gating_pulse:inst\|counter_small_Get\[3\]\" (period= 37.54 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.656 ns + Longest register register " "Info: + Longest register to register delay is 3.656 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns my_DFF:inst13\|Q 1 REG LCFF_X68_Y30_N3 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X68_Y30_N3; Fanout = 8; REG Node = 'my_DFF:inst13\|Q'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { my_DFF:inst13|Q } "NODE_NAME" } } { "my_DFF.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/my_DFF.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.206 ns) 0.668 ns gating_pulse:inst\|counter_small_Get\[4\]~638 2 COMB LCCOMB_X68_Y30_N0 5 " "Info: 2: + IC(0.462 ns) + CELL(0.206 ns) = 0.668 ns; Loc. = LCCOMB_X68_Y30_N0; Fanout = 5; COMB Node = 'gating_pulse:inst\|counter_small_Get\[4\]~638'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.668 ns" { my_DFF:inst13|Q gating_pulse:inst|counter_small_Get[4]~638 } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.206 ns) 1.268 ns gating_pulse:inst\|counter_small_Get\[4\]~644 3 COMB LCCOMB_X68_Y30_N30 2 " "Info: 3: + IC(0.394 ns) + CELL(0.206 ns) = 1.268 ns; Loc. = LCCOMB_X68_Y30_N30; Fanout = 2; COMB Node = 'gating_pulse:inst\|counter_small_Get\[4\]~644'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.600 ns" { gating_pulse:inst|counter_small_Get[4]~638 gating_pulse:inst|counter_small_Get[4]~644 } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.206 ns) 1.834 ns gating_pulse:inst\|counter_small_Get\[4\]~646 4 COMB LCCOMB_X68_Y30_N26 5 " "Info: 4: + IC(0.360 ns) + CELL(0.206 ns) = 1.834 ns; Loc. = LCCOMB_X68_Y30_N26; Fanout = 5; COMB Node = 'gating_pulse:inst\|counter_small_Get\[4\]~646'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.566 ns" { gating_pulse:inst|counter_small_Get[4]~644 gating_pulse:inst|counter_small_Get[4]~646 } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.967 ns) + CELL(0.855 ns) 3.656 ns gating_pulse:inst\|counter_small_Get\[3\] 5 REG LCFF_X66_Y30_N19 4 " "Info: 5: + IC(0.967 ns) + CELL(0.855 ns) = 3.656 ns; Loc. = LCFF_X66_Y30_N19; Fanout = 4; REG Node = 'gating_pulse:inst\|counter_small_Get\[3\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.822 ns" { gating_pulse:inst|counter_small_Get[4]~646 gating_pulse:inst|counter_small_Get[3] } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.473 ns ( 40.29 % ) " "Info: Total cell delay = 1.473 ns ( 40.29 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.183 ns ( 59.71 % ) " "Info: Total interconnect delay = 2.183 ns ( 59.71 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.656 ns" { my_DFF:inst13|Q gating_pulse:inst|counter_small_Get[4]~638 gating_pulse:inst|counter_small_Get[4]~644 gating_pulse:inst|counter_small_Get[4]~646 gating_pulse:inst|counter_small_Get[3] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "3.656 ns" { my_DFF:inst13|Q gating_pulse:inst|counter_small_Get[4]~638 gating_pulse:inst|counter_small_Get[4]~644 gating_pulse:inst|counter_small_Get[4]~646 gating_pulse:inst|counter_small_Get[3] } { 0.000ns 0.462ns 0.394ns 0.360ns 0.967ns } { 0.000ns 0.206ns 0.206ns 0.206ns 0.855ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-14.850 ns - Smallest " "Info: - Smallest clock skew is -14.850 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M destination 6.733 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_40M\" to destination register is 6.733 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK_40M 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'CLK_40M'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_40M } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.135 ns) + CELL(0.000 ns) 1.235 ns CLK_40M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK_40M~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.135 ns" { CLK_40M CLK_40M~clkctrl } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.431 ns) + CELL(0.970 ns) 3.636 ns div_mult:inst8\|counter\[0\] 3 REG LCFF_X50_Y1_N25 4 " "Info: 3: + IC(1.431 ns) + CELL(0.970 ns) = 3.636 ns; Loc. = LCFF_X50_Y1_N25; Fanout = 4; REG Node = 'div_mult:inst8\|counter\[0\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.401 ns" { CLK_40M~clkctrl div_mult:inst8|counter[0] } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.000 ns) 4.645 ns div_mult:inst8\|counter\[0\]~clkctrl 4 COMB CLKCTRL_G12 40 " "Info: 4: + IC(1.009 ns) + CELL(0.000 ns) = 4.645 ns; Loc. = CLKCTRL_G12; Fanout = 40; COMB Node = 'div_mult:inst8\|counter\[0\]~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.422 ns) + CELL(0.666 ns) 6.733 ns gating_pulse:inst\|counter_small_Get\[3\] 5 REG LCFF_X66_Y30_N19 4 " "Info: 5: + IC(1.422 ns) + CELL(0.666 ns) = 6.733 ns; Loc. = LCFF_X66_Y30_N19; Fanout = 4; REG Node = 'gating_pulse:inst\|counter_small_Get\[3\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.088 ns" { div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_Get[3] } "NODE_NAME" } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 110 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.736 ns ( 40.64 % ) " "Info: Total cell delay = 2.736 ns ( 40.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.997 ns ( 59.36 % ) " "Info: Total interconnect delay = 3.997 ns ( 59.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.733 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_Get[3] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "6.733 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_Get[3] } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.422ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_40M source 21.583 ns - Longest register " "Info: - Longest clock path from clock \"CLK_40M\" to source register is 21.583 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.100 ns) 1.100 ns CLK_40M 1 CLK PIN_T2 1 " "Info: 1: + IC(0.000 ns) + CELL(1.100 ns) = 1.100 ns; Loc. = PIN_T2; Fanout = 1; CLK Node = 'CLK_40M'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK_40M } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.135 ns) + CELL(0.000 ns) 1.235 ns CLK_40M~clkctrl 2 COMB CLKCTRL_G3 9 " "Info: 2: + IC(0.135 ns) + CELL(0.000 ns) = 1.235 ns; Loc. = CLKCTRL_G3; Fanout = 9; COMB Node = 'CLK_40M~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.135 ns" { CLK_40M CLK_40M~clkctrl } "NODE_NAME" } } { "CH8_Matrix.bdf" "" { Schematic "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/CH8_Matrix.bdf" { { -392 -616 -448 -376 "CLK_40M" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.431 ns) + CELL(0.970 ns) 3.636 ns div_mult:inst8\|counter\[8\] 3 REG LCFF_X50_Y1_N19 2 " "Info: 3: + IC(1.431 ns) + CELL(0.970 ns) = 3.636 ns; Loc. = LCFF_X50_Y1_N19; Fanout = 2; REG Node = 'div_mult:inst8\|counter\[8\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.401 ns" { CLK_40M~clkctrl div_mult:inst8|counter[8] } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.009 ns) + CELL(0.000 ns) 4.645 ns div_mult:inst8\|counter\[8\]~clkctrl 4 COMB CLKCTRL_G13 9 " "Info: 4: + IC(1.009 ns) + CELL(0.000 ns) = 4.645 ns; Loc. = CLKCTRL_G13; Fanout = 9; COMB Node = 'div_mult:inst8\|counter\[8\]~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { div_mult:inst8|counter[8] div_mult:inst8|counter[8]~clkctrl } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.441 ns) + CELL(0.970 ns) 7.056 ns div_mult:inst16\|counter\[8\] 5 REG LCFF_X94_Y26_N25 2 " "Info: 5: + IC(1.441 ns) + CELL(0.970 ns) = 7.056 ns; Loc. = LCFF_X94_Y26_N25; Fanout = 2; REG Node = 'div_mult:inst16\|counter\[8\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.411 ns" { div_mult:inst8|counter[8]~clkctrl div_mult:inst16|counter[8] } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.816 ns) + CELL(0.000 ns) 7.872 ns div_mult:inst16\|counter\[8\]~clkctrl 6 COMB CLKCTRL_G7 2 " "Info: 6: + IC(0.816 ns) + CELL(0.000 ns) = 7.872 ns; Loc. = CLKCTRL_G7; Fanout = 2; COMB Node = 'div_mult:inst16\|counter\[8\]~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.816 ns" { div_mult:inst16|counter[8] div_mult:inst16|counter[8]~clkctrl } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.478 ns) + CELL(0.970 ns) 10.320 ns div_mult:inst23\|counter\[1\] 7 REG LCFF_X47_Y50_N1 2 " "Info: 7: + IC(1.478 ns) + CELL(0.970 ns) = 10.320 ns; Loc. = LCFF_X47_Y50_N1; Fanout = 2; REG Node = 'div_mult:inst23\|counter\[1\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.448 ns" { div_mult:inst16|counter[8]~clkctrl div_mult:inst23|counter[1] } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.996 ns) + CELL(0.000 ns) 11.316 ns div_mult:inst23\|counter\[1\]~clkctrl 8 COMB CLKCTRL_G11 4 " "Info: 8: + IC(0.996 ns) + CELL(0.000 ns) = 11.316 ns; Loc. = CLKCTRL_G11; Fanout = 4; COMB Node = 'div_mult:inst23\|counter\[1\]~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.996 ns" { div_mult:inst23|counter[1] div_mult:inst23|counter[1]~clkctrl } "NODE_NAME" } } { "div_mult.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div_mult.v" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.451 ns) + CELL(0.970 ns) 13.737 ns div5:inst20\|state\[0\] 9 REG LCFF_X48_Y1_N31 5 " "Info: 9: + IC(1.451 ns) + CELL(0.970 ns) = 13.737 ns; Loc. = LCFF_X48_Y1_N31; Fanout = 5; REG Node = 'div5:inst20\|state\[0\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.421 ns" { div_mult:inst23|counter[1]~clkctrl div5:inst20|state[0] } "NODE_NAME" } } { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.451 ns) + CELL(0.206 ns) 14.394 ns div5:inst20\|clk_out 10 COMB LCCOMB_X48_Y1_N16 1 " "Info: 10: + IC(0.451 ns) + CELL(0.206 ns) = 14.394 ns; Loc. = LCCOMB_X48_Y1_N16; Fanout = 1; COMB Node = 'div5:inst20\|clk_out'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.657 ns" { div5:inst20|state[0] div5:inst20|clk_out } "NODE_NAME" } } { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.088 ns) + CELL(0.000 ns) 15.482 ns div5:inst20\|clk_out~clkctrl 11 COMB CLKCTRL_G14 4 " "Info: 11: + IC(1.088 ns) + CELL(0.000 ns) = 15.482 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'div5:inst20\|clk_out~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.088 ns" { div5:inst20|clk_out div5:inst20|clk_out~clkctrl } "NODE_NAME" } } { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.428 ns) + CELL(0.970 ns) 17.880 ns div5:inst19\|state\[0\] 12 REG LCFF_X49_Y1_N19 5 " "Info: 12: + IC(1.428 ns) + CELL(0.970 ns) = 17.880 ns; Loc. = LCFF_X49_Y1_N19; Fanout = 5; REG Node = 'div5:inst19\|state\[0\]'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.398 ns" { div5:inst20|clk_out~clkctrl div5:inst19|state[0] } "NODE_NAME" } } { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 8 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.206 ns) 18.540 ns div5:inst19\|clk_out 13 COMB LCCOMB_X49_Y1_N2 1 " "Info: 13: + IC(0.454 ns) + CELL(0.206 ns) = 18.540 ns; Loc. = LCCOMB_X49_Y1_N2; Fanout = 1; COMB Node = 'div5:inst19\|clk_out'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.660 ns" { div5:inst19|state[0] div5:inst19|clk_out } "NODE_NAME" } } { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.954 ns) + CELL(0.000 ns) 19.494 ns div5:inst19\|clk_out~clkctrl 14 COMB CLKCTRL_G15 2 " "Info: 14: + IC(0.954 ns) + CELL(0.000 ns) = 19.494 ns; Loc. = CLKCTRL_G15; Fanout = 2; COMB Node = 'div5:inst19\|clk_out~clkctrl'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.954 ns" { div5:inst19|clk_out div5:inst19|clk_out~clkctrl } "NODE_NAME" } } { "div5.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/div5.v" 4 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.423 ns) + CELL(0.666 ns) 21.583 ns my_DFF:inst13\|Q 15 REG LCFF_X68_Y30_N3 8 " "Info: 15: + IC(1.423 ns) + CELL(0.666 ns) = 21.583 ns; Loc. = LCFF_X68_Y30_N3; Fanout = 8; REG Node = 'my_DFF:inst13\|Q'" { } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.089 ns" { div5:inst19|clk_out~clkctrl my_DFF:inst13|Q } "NODE_NAME" } } { "my_DFF.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/my_DFF.v" 3 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.028 ns ( 32.56 % ) " "Info: Total cell delay = 7.028 ns ( 32.56 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.555 ns ( 67.44 % ) " "Info: Total interconnect delay = 14.555 ns ( 67.44 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "21.583 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[8] div_mult:inst8|counter[8]~clkctrl div_mult:inst16|counter[8] div_mult:inst16|counter[8]~clkctrl div_mult:inst23|counter[1] div_mult:inst23|counter[1]~clkctrl div5:inst20|state[0] div5:inst20|clk_out div5:inst20|clk_out~clkctrl div5:inst19|state[0] div5:inst19|clk_out div5:inst19|clk_out~clkctrl my_DFF:inst13|Q } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "21.583 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[8] div_mult:inst8|counter[8]~clkctrl div_mult:inst16|counter[8] div_mult:inst16|counter[8]~clkctrl div_mult:inst23|counter[1] div_mult:inst23|counter[1]~clkctrl div5:inst20|state[0] div5:inst20|clk_out div5:inst20|clk_out~clkctrl div5:inst19|state[0] div5:inst19|clk_out div5:inst19|clk_out~clkctrl my_DFF:inst13|Q } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.441ns 0.816ns 1.478ns 0.996ns 1.451ns 0.451ns 1.088ns 1.428ns 0.454ns 0.954ns 1.423ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.206ns 0.000ns 0.666ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.733 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_Get[3] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "6.733 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_Get[3] } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.422ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "21.583 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[8] div_mult:inst8|counter[8]~clkctrl div_mult:inst16|counter[8] div_mult:inst16|counter[8]~clkctrl div_mult:inst23|counter[1] div_mult:inst23|counter[1]~clkctrl div5:inst20|state[0] div5:inst20|clk_out div5:inst20|clk_out~clkctrl div5:inst19|state[0] div5:inst19|clk_out div5:inst19|clk_out~clkctrl my_DFF:inst13|Q } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "21.583 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[8] div_mult:inst8|counter[8]~clkctrl div_mult:inst16|counter[8] div_mult:inst16|counter[8]~clkctrl div_mult:inst23|counter[1] div_mult:inst23|counter[1]~clkctrl div5:inst20|state[0] div5:inst20|clk_out div5:inst20|clk_out~clkctrl div5:inst19|state[0] div5:inst19|clk_out div5:inst19|clk_out~clkctrl my_DFF:inst13|Q } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.441ns 0.816ns 1.478ns 0.996ns 1.451ns 0.451ns 1.088ns 1.428ns 0.454ns 0.954ns 1.423ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.206ns 0.000ns 0.666ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" { } { { "my_DFF.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/my_DFF.v" 3 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" { } { { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 110 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "my_DFF.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/my_DFF.v" 3 -1 0 } } { "gating_pulse.v" "" { Text "C:/Documents and Settings/Administrator.LEFAN/桌面/8通道调试程序/4通道800K加判断(修改方案后)/gating_pulse.v" 110 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.656 ns" { my_DFF:inst13|Q gating_pulse:inst|counter_small_Get[4]~638 gating_pulse:inst|counter_small_Get[4]~644 gating_pulse:inst|counter_small_Get[4]~646 gating_pulse:inst|counter_small_Get[3] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "3.656 ns" { my_DFF:inst13|Q gating_pulse:inst|counter_small_Get[4]~638 gating_pulse:inst|counter_small_Get[4]~644 gating_pulse:inst|counter_small_Get[4]~646 gating_pulse:inst|counter_small_Get[3] } { 0.000ns 0.462ns 0.394ns 0.360ns 0.967ns } { 0.000ns 0.206ns 0.206ns 0.206ns 0.855ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "6.733 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_Get[3] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "6.733 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[0] div_mult:inst8|counter[0]~clkctrl gating_pulse:inst|counter_small_Get[3] } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.422ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.666ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "21.583 ns" { CLK_40M CLK_40M~clkctrl div_mult:inst8|counter[8] div_mult:inst8|counter[8]~clkctrl div_mult:inst16|counter[8] div_mult:inst16|counter[8]~clkctrl div_mult:inst23|counter[1] div_mult:inst23|counter[1]~clkctrl div5:inst20|state[0] div5:inst20|clk_out div5:inst20|clk_out~clkctrl div5:inst19|state[0] div5:inst19|clk_out div5:inst19|clk_out~clkctrl my_DFF:inst13|Q } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "21.583 ns" { CLK_40M CLK_40M~combout CLK_40M~clkctrl div_mult:inst8|counter[8] div_mult:inst8|counter[8]~clkctrl div_mult:inst16|counter[8] div_mult:inst16|counter[8]~clkctrl div_mult:inst23|counter[1] div_mult:inst23|counter[1]~clkctrl div5:inst20|state[0] div5:inst20|clk_out div5:inst20|clk_out~clkctrl div5:inst19|state[0] div5:inst19|clk_out div5:inst19|clk_out~clkctrl my_DFF:inst13|Q } { 0.000ns 0.000ns 0.135ns 1.431ns 1.009ns 1.441ns 0.816ns 1.478ns 0.996ns 1.451ns 0.451ns 1.088ns 1.428ns 0.454ns 0.954ns 1.423ns } { 0.000ns 1.100ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.000ns 0.970ns 0.206ns 0.000ns 0.970ns 0.206ns 0.000ns 0.666ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -