ch8_matrix.fit.smsg

用fpga+usb显现的4通道800K的数据采集方案。

Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Wed Jun 04 13:12:09 2008
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off CH8_Matrix -c CH8_Matrix
Info: Selected device EP2C70F896C8 for design "CH8_Matrix"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: The Fitter has identified 1 logical partitions of which 0 have a previous placement to use
    Info: Previous placement does not exist for 249 of 249 atoms in partition Top
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C70F896I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location G7
    Info: Pin ~nCSO~ is reserved at location K9
    Info: Pin ~LVDS69n/DEV_CLRn~ is reserved at location D4
Warning: No exact pin location assignment(s) for 2 pins of 46 total pins
    Info: Pin TB_MIX not assigned to an exact location on the device
    Info: Pin flagb not assigned to an exact location on the device
Info: Automatically promoted node CLK_40M (placed in PIN T2 (CLK2, LVDSCLK1p, Input))
    Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3
Info: Automatically promoted node div_mult:inst8|counter[0] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node div_mult:inst8|counter[1]~41
        Info: Destination node div_mult:inst8|counter[0]~50
Info: Automatically promoted node gating_pulse:inst|Get_CLK 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node div_mult:inst8|counter[8] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node div_mult:inst8|counter[8]~34
Info: Automatically promoted node div5:inst20|clk_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node div_mult:inst23|counter[1] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node div_mult:inst23|counter[1]~34
Info: Automatically promoted node div5:inst19|clk_out 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
Info: Automatically promoted node div_mult:inst16|counter[8] 
    Info: Automatically promoted destinations to use location or clock signal Global Clock
    Info: Following destination nodes may be non-global or may not use global or regional clocks
        Info: Destination node div_mult:inst16|counter[8]~34
Info: Starting register packing
Info: Finished register packing: elapsed time is 00:00:00
    Extra Info: No registers were packed into other blocks
Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
    Info: Number of I/O pins in group: 2 (unused VREF, 3.30 VCCIO, 1 input, 1 output, 0 bidirectional)
        Info: I/O standards used: 3.3-V LVTTL.
Info: I/O bank details before I/O pin placement
    Info: Statistics of I/O banks
        Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 2 total pin(s) used --  83 pins available
        Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 2 total pin(s) used --  77 pins available
        Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 8 total pin(s) used --  64 pins available
        Info: I/O bank number 4 does not use VREF pins and has 3.30V VCCIO pins. 20 total pin(s) used --  54 pins available
        Info: I/O bank number 5 does not use VREF pins and has 3.30V VCCIO pins. 15 total pin(s) used --  70 pins available
        Info: I/O bank number 6 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  81 pins available
        Info: I/O bank number 7 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  74 pins available
        Info: I/O bank number 8 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  72 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 4.412 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X68_Y30; Fanout = 8; REG Node = 'my_DFF:inst13|Q'
    Info: 2: + IC(0.230 ns) + CELL(0.650 ns) = 0.880 ns; Loc. = LAB_X68_Y30; Fanout = 5; COMB Node = 'gating_pulse:inst|counter_small_Get[4]~638'
    Info: 3: + IC(0.161 ns) + CELL(0.651 ns) = 1.692 ns; Loc. = LAB_X68_Y30; Fanout = 2; COMB Node = 'gating_pulse:inst|counter_small_Get[4]~644'
    Info: 4: + IC(0.188 ns) + CELL(0.616 ns) = 2.496 ns; Loc. = LAB_X68_Y30; Fanout = 5; COMB Node = 'gating_pulse:inst|counter_small_Get[4]~646'
    Info: 5: + IC(1.061 ns) + CELL(0.855 ns) = 4.412 ns; Loc. = LAB_X66_Y30; Fanout = 4; REG Node = 'gating_pulse:inst|counter_small_Get[3]'
    Info: Total cell delay = 2.772 ns ( 62.83 % )
    Info: Total interconnect delay = 1.640 ns ( 37.17 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%
    Info: The peak interconnect region extends from location X84_Y39 to location X95_Y51
Info: Fitter routing operations ending: elapsed time is 00:00:01
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Following 2 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin RDY0 has VCC driving its datain port
    Info: Pin PDWN8 has GND driving its datain port
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
    Info: Allocated 291 megabytes of memory during processing
    Info: Processing ended: Wed Jun 04 13:12:52 2008
    Info: Elapsed time: 00:00:43