dds_straight_new.v

来自「用fpga+usb显现的4通道800K的数据采集方案。」· Verilog 代码 · 共 15 行

module DDS_straight_new(PC4,PC5,PC6,PC7,PC0,CLK2,RST_DDS,CLK1,SDIO,Update);
input PC4,PC5,PC6,PC7,PC0;
//input PS10_flag;

output CLK2,RST_DDS,CLK1,SDIO,Update;
//output PS10,PS20;

//reg PS10,PS20;
//reg[3:0] counter;
assign CLK2=PC4;
assign RST_DDS=PC5;
assign CLK1=PC6;
assign SDIO=PC7;
assign Update=PC0;
endmodule