update_pulse.v

来自「用fpga+usb显现的4通道800K的数据采集方案。」· Verilog 代码 · 共 46 行

module update_pulse(PS_flag,CLK,update1,update2);   //TP为门控脉冲，TB为压地波脉冲
input PS_flag,CLK;                          //FM为AD9954触发脉冲
output update1,update2;                    //2800D＝6D60H

reg update1,update2;

reg temp_FM;
reg[17:0] counter;
//-------------------------------


always@(posedge CLK)//10M 的时钟
begin
 if(PS_flag)
  begin
    if(counter==211399)counter<=0;//周期是21.14ms
    else counter<=counter+1;
  end
 else
  begin
    counter<=0;
  end
end

always@(posedge CLK)
begin
 update1<=temp_FM;
 update2<=temp_FM;
end

always@(counter or PS_flag)
begin
 if(PS_flag)
   begin
    if((counter>=1)&&(counter<=79000))temp_FM<=1;//扫频触发脉冲和TP对齐 
    else temp_FM<=0;
   end
 else
  begin
    temp_FM<=0;
  end
end

endmodule