hm_address.v

来自「用fpga+usb显现的4通道800K的数据采集方案。」· Verilog 代码 · 共 20 行

module HM_address(CLK,RST,address);

input RST,CLK;
output[1:0] address;
reg[1:0] counter;

assign address=counter;
always@(posedge CLK or posedge RST)
begin
 if(RST)
  begin
   counter<=2'b00;
  end
 else
  begin
   counter<=counter+2'b01;
  end  
end
endmodule