uart16bitloopback.txt

this is a implementation of the 16 bit loop back in vhdl

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity uart16bitloopback is   
port(clock : in std_logic;
	 sin : in std_logic;
     DOUT : out std_logic_vector(15 downto 0);
      sout  : inout std_logic);				
end uart16bitloopback;
architecture ar_uart16bitloopback of uart16bitloopback is
type state_type is (s0,s1,s2);
signal state:state_type;							
--type state1_type is (s0,s1,s2);
signal state1:state_type;
signal b,startsig: std_logic:= '0';
signal reset,rxclockx16,txclockx1616 : std_logic:='1';
signal count:std_logic_vector(0 to 8):="000000000";
signal count2:std_logic_vector(0 to 12):="0000000000000";
signal n:integer range 0 to 20;
signal j,l:integer range 0 to 30:=0;
signal TSR,RSR : std_logic_vector(15 downto 0):= "0000000000000000";
signal count4,count5,count6,count7:  integer range 0 to 30 :=0;
begin
--receiver clock
process(clock,reset,startsig)
begin
if clock'event and clock='1' and reset ='0' then
      count <=count+1;
      if count <= "010100010" then  -- for 16x9600 bps from 50Mhz , 326 
	  rxclockx16<='1';
	  elsif count > "010100010" and count <= "101000101" then
	  rxclockx16<='0';
	  else
	  count<=(others=>'0');
	  end if;	
end if;
end process;

--transmitter clock	 
process(clock,reset)
begin 
if  clock'event and clock ='1' and reset = '0' then
    count2 <=count2+1;
	if count2 <= "0101000101100" then  -- for 16 times the clockx16(Baud rate of 9600)
	txclockx1616<='1';
	elsif count2> "0101000101100" and count2 <= "1010001011000" then
	txclockx1616<='0';
	else
	count2 <=(others=>'0');
end if;	
end if;
end process;

--counting receiver clocks
process(rxclockx16,startsig)
begin
if startsig = '1' and sin = '1' then
    count7 <= 0;
elsif rxclockx16'event and rxclockx16 ='1' then
   if count7 < 16 and (startsig = '0' or sin = '0') then
	  count7 <= count7 +1;
	elsif (startsig = '1' or count7 = 16)  then
	   count7 <= 1;
   end if;
end if;
end process;

  

 --autoreset
 process(clock)
 
 begin
 if clock'event and clock ='1' then
   if  n <= 1 then 
    reset <= '1';
	 n <= n+1;
   else
    reset <= '0';
   if count5 = 4 then
      n <= 0;
	end if;    
   end if;
	if count4 = 2 then
	TSR <= RSR;
	end if;
	if count7 = 7 then
       b <= sin;
    end if;
   end if;
  end process;

--receiver statemachine 

process(rxclockx16,reset,state)
begin  
if reset = '1' then
  count4 <= 0;

elsif rxclockx16'event and rxclockx16 = '1'  and reset = '0' and  
     (count7 = 2 or count7 = 13 ) and count4 < 2 then
  case state is
   --idle state
  when s0 =>
     if (sin = '0') then
      startsig <= '0';
	  DOUT <= (others => '0');
	end if;
	  if (count7 = 13 and sin = '0') then 
	     state <= s1;
	  else
	    state <= s0;
		startsig <= '1';
	  end if;
	

  --shift state
  when s1=>
    if (count7 = 13) then 
     if (l < 8) then
        RSR(15) <= b;
	     for i in  0 to 14 loop
         RSR(i) <= RSR(i+1);
         end loop;
            l <= l+1;
        if (l < 7) then
            state <= s1;
         else
          state <= s2;
		  l <= 0;
         end if;
	end if;
  end if;

  
  --stopstate 
  when s2 =>
    DOUT(15 DOWNTO 8) <= RSR(7 DOWNTO 0);
	DOUT(7 DOWNTO 0) <= RSR(15 DOWNTO 8);
	if sin = '0' then
	  state <= s2;
	 end if;
    if sin = '1'  then
	 if (count7 = 13) then
    	 if(count4 < 2) then
	        state <= s0;
			startsig <= '1';
	     end if;   
		   count4 <= count4+1;
	 end if;
    end if;
  end case;
  end if;
end process;

--transmitter state machine
process(TSR,txclockx1616,reset,state1)
begin
if reset = '1' then
    count5 <= 0;
	j <= 0;
elsif count4 < 2 then
  sout <= '1';    
elsif  txclockx1616'event and txclockx1616 = '1' 
      and reset ='0' and count5 < 4 and count4 = 2 then 
   case state1 is
   --start state
   when s0 =>  
        sout <= '0';
		 state1 <=s1;
         count6 <= 0;  
  --shift state    
   when s1=>  
    if(count5 = 0) then 
     if (j < 8) then
      sout <= TSR(j);
         j<= j+1;
     if (j < 7) then
	   state1 <=s1;
     else
	  j <= 0;
      state1 <= s2;
      end if;
     end if;
    elsif(count5 = 2) then
	 if ( j < 16) then
      sout <= TSR(j);
         j <= j+1;
     if (j < 15) then
	   state1 <=s1;
     else
	   j <= 0;
	   state1 <=s2 ;
     end if;
 	 end if;
    end if;

  --stop1bit state  
   when s2=>
        sout <= '1';
    if count5 < 4 and count6 = 1 then
	    j <= 8;
	   state1 <= s0;
	else
	   state1 <= s2;
     end if;
	   count5 <= count5 +1;
	   count6 <= count6+1;
   end case;
end if;
end process;  
end ar_uart16bitloopback;