top_uart.v

uart的代码

////////////////////////////////////////////////////////////////////////////////
// *****************************************************************************
// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
// *                                                                           *
// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
// *  to other documents, or disclosed to third parties, or used for any       *
// *  purpose other than that for which it was obtained, without the prior     *
// *  written consent of RicHic Inc.                                           *
// *             (c) 2003, 2004, 2005 RicHic Inc.                              *
// *                All rights reserved                                        * 
// *****************************************************************************
//
// (C) 2004 [e-mail];     [e-mail]
//     http://www.richic.com
//
////////////////////////////////////////////////////////////////////////////////

module top_uart(
    clk,
    rst_n,
    rs232_r1,
    rs232_r2,
    rs232_t1,
    rs232_t2,
    rx1_data,
    rx2_data
    
    );
input           clk ;
input           rst_n;// synthesis attribute clock_buffer of rst_n is ibufg;
input           rs232_r1;
input           rs232_r2;
output          rs232_t1;
output          rs232_t2;
output  [7:0]   rx1_data;
output  [7:0]   rx2_data;


wire            txd;

wire        clk16x  ;
uart_clk_50m uart_clk_50m_inst(
    .clk     (clk    ),
    .rst_n   (rst_n  ),
    
    .uart_clk16x(clk16x)
    ); 

wire        [7:0]   dout1,dout2;
wire                data_ready1,data_ready2;
wire                framing_error1,framing_error2;
wire                parity_error1,parity_error2;

uart_rx  uart_rx_inst1(
    .clk16x         (clk16x ),
    .rst            (!rst_n ),
    .rxd            (rs232_r1),
    .dout           (rx1_data),
    .data_ready     (data_ready1     ),
    .framing_error  (framing_error1  ),
    .parity_error   (parity_error1   )
    ) ;

uart_rx  uart_rx_inst2(
    .clk16x         (clk16x ),
    .rst            (!rst_n ),
    .rxd            (rs232_r2),
    .dout           (rx2_data   ),
    .data_ready     (data_ready2    ),
    .framing_error  (framing_error2  ),
    .parity_error   (parity_error2   )
    ) ;


wire    tbre;
wire    tsre;
wire    wrn;
reg     [13:0]   clk16x_cnt;
always @ ( posedge clk16x or negedge rst_n )
    if ( !rst_n )
        clk16x_cnt <= 14'd0;
    else
        clk16x_cnt <= clk16x_cnt + 1'b1;
        
assign  wrn = clk16x_cnt[11] ;

wire    sdo;
reg     [8:0]   char_cnt;
wire    [7:0]   data;
wire    [7:0]   din = {data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]};
uart_tx uart_tx_inst(
    .rst            (!rst_n ),
    .clk16x         (clk16x ),
    .din            (din    ),
    .tbre           (tbre   ),
    .tsre           (tsre   ),
    .wrn            (wrn    ),   
    .sdo            (sdo    ),
    .txd            (txd    )
    ) ;

always @ ( posedge clk16x or negedge rst_n )
    if (!rst_n )
        char_cnt <= 9'd0;
    else if (clk16x_cnt[11:0] == 12'hf00)
        char_cnt <= char_cnt + 1'b1;
 

uart_char_rom  char_rom_inst (
    .addr   (char_cnt),
    .data   (data)
    );         

assign  rs232_t1 = txd;
assign  rs232_t2 = txd;

endmodule