uart_tx.v

uart的代码

////////////////////////////////////////////////////////////////////////////////
// *****************************************************************************
// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
// *                                                                           *
// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
// *  to other documents, or disclosed to third parties, or used for any       *
// *  purpose other than that for which it was obtained, without the prior     *
// *  written consent of RicHic Inc.                                           *
// *             (c) 2003, 2004, 2005 RicHic Inc.                              *
// *                All rights reserved                                        * 
// *****************************************************************************
//
// (C) 2004 [e-mail];     [e-mail]
//     http://www.richic.com
//
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns / 1 ns

module uart_tx(
    rst,
    clk16x,
    din,
    tbre,
    tsre,
    wrn,
    sdo,
    txd
    ) ;

output tbre ;
output tsre ;
output sdo ;
input [7:0] din ;
input rst ;
input clk16x ;
input wrn ;
output  txd;
reg tbre ;
reg tsre ;
reg clk1x_enable ;
reg [7:0] tsr ;
reg [7:0] tbr ;

reg parity ;

reg[3:0] clkdiv ;
wire clk1x ;
reg sdo ;
reg [3:0] no_bits_sent ;
reg wrn1 ;
reg wrn2 ;

always @(posedge clk16x or posedge rst)
begin
if (rst)
begin
wrn1 <= 1'b1 ;
wrn2 <= 1'b1 ;
end
else 
begin
wrn1 <= wrn ;
wrn2 <= wrn1 ;
end
end


always @(posedge clk16x or posedge rst)
begin
if (rst)
begin
tbre <= 1'b0 ;
clk1x_enable <= 1'b0 ;
end
else if (!wrn1 && wrn2) 
begin
clk1x_enable <= 1'b1 ;
tbre <= 1'b1 ;
end
else if (no_bits_sent == 4'b0010)
tbre <= 1'b1 ;
else if (no_bits_sent == 4'b1101)
begin
clk1x_enable <= 1'b0 ;
tbre <= 1'b0 ;
end
end

always @(negedge wrn or posedge rst)
begin
if (rst)
tbr = 8'b0 ;
else
tbr = din ;
end

always @(posedge clk16x or posedge rst)
begin
if (rst)
clkdiv = 4'b0 ; 
else if (clk1x_enable)
clkdiv = clkdiv + 1 ;
end

assign clk1x = clkdiv[3] ;

always @(negedge clk1x or posedge rst)
if (rst)
begin
sdo <= 1'b1 ;
tsre <= 1'b1 ;
parity <= 1'b1 ;
tsr <= 8'b0 ;
end
else
begin
if (no_bits_sent == 4'b0001)
begin
tsr <= tbr ;
tsre <= 1'b0 ;
end
else if (no_bits_sent == 4'b0010)
begin
sdo <= 1'b0 ;
end
else
if ((no_bits_sent >= 4'b0011) && (no_bits_sent <= 4'b1010))
begin
tsr[7:1] <= tsr[6:0] ;
tsr[0] <= 1'b0 ;
sdo <= tsr[7] ;
parity <= parity ^ tsr[7] ;
end
else if (no_bits_sent == 4'b1011)
begin
sdo <= parity ;
end
else if (no_bits_sent == 4'b1100)
begin
sdo <= 1'b1 ;
tsre <= 1'b1 ;
end

end

always @(posedge clk1x or negedge clk1x_enable )
if (!clk1x_enable)
no_bits_sent = 4'b0000 ;
else
no_bits_sent = no_bits_sent + 1 ;

reg    wr_n_z;
reg    wr_n_zz;

wire    wr_n_pulse = !wr_n_z && wr_n_zz;
reg     [3:0]   tx_clk_cnt;
always @ ( posedge clk16x or posedge rst )
    if ( rst )
        tx_clk_cnt <= 4'd0;
    else
        tx_clk_cnt <= tx_clk_cnt + 1'b1;

wire    tx_clk = tx_clk_cnt[3];

always @(posedge tx_clk or posedge rst)
begin
if (rst)
begin
wr_n_z <= 1'b1 ;
wr_n_zz <= 1'b1 ;
end
else 
begin
wr_n_z <= wrn ;
wr_n_zz <= wr_n_z ;
end
end

 
reg     [7:0]   din_latch1;
wire    rst_n = !rst;
always @ ( posedge tx_clk or negedge rst_n )        
    if ( !rst_n )
        din_latch1 <= 8'd0;
    else if ( wr_n_pulse)
        din_latch1 <= din;
        
reg [3:0]   sent_bit;
always @ ( posedge tx_clk or negedge rst_n )
    if ( !rst_n )
        sent_bit <= 4'd0;
    else if ( wr_n_pulse )
        sent_bit <= 4'd0;
    else if (sent_bit == 4'd15)
        sent_bit <= 4'd15;
    else
        sent_bit <= sent_bit + 1'b1;

reg     txd;
reg     [7:0]   din_latch2;
reg     parity_bit;
always @ ( posedge tx_clk or negedge rst_n )
    if ( !rst_n )
        begin
            txd <= 1'b1;
            din_latch2 <= 8'd0;
            parity_bit <= 1'b1;
        end
    else if ( sent_bit == 4'd1 )
        begin
            din_latch2 <= din_latch1;
            parity_bit <= 1'b1;
        end    
    else if ( sent_bit == 4'd2 )
        txd <= 1'b0;    
    else if ((sent_bit >= 4'd3) && (sent_bit <= 4'd10))
        begin
            txd <= din_latch2[7];
            parity_bit <= parity_bit ^ din_latch2[7];
            din_latch2[7:0] <= {din_latch2[6:0],1'b0};            
        end    
    else if ( sent_bit == 4'd11 )
        txd <= parity_bit;
    else if ( sent_bit == 4'd12)
        txd <= 1'b1;        
               
endmodule