uart_clk_50m.v

uart的代码

////////////////////////////////////////////////////////////////////////////////
// *****************************************************************************
// *  RICHIC CONFIDENTIAL PROPRIETARY NOTE                                     *
// *                                                                           *
// *  This software contains information confidential and proprietary to       *
// *  RicHic Inc.It shall not be reproduced in whole or in part or transferred *
// *  to other documents, or disclosed to third parties, or used for any       *
// *  purpose other than that for which it was obtained, without the prior     *
// *  written consent of RicHic Inc.                                           *
// *             (c) 2003, 2004, 2005 RicHic Inc.                              *
// *                All rights reserved                                        * 
// *****************************************************************************
//
// (C) 2004 [e-mail];     [e-mail]
//     http://www.richic.com
//
////////////////////////////////////////////////////////////////////////////////

module uart_clk_50m(
    clk     ,
    rst_n   ,
    
    uart_clk16x
    );

input   clk     ;
input   rst_n   ;
output  uart_clk16x;

//Select transceiver 4800Buad/s
// 325.520833333333333333333

reg     [8:0]   clk_cnt ;
reg             pulse   ;

always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
        clk_cnt <= 9'd0;
    else if( pulse && (clk_cnt == 9'd325))
        clk_cnt <= 9'd0;
    else if ((!pulse) && (clk_cnt== 9'd324))
        clk_cnt <= 9'd0;
    else
        clk_cnt <= clk_cnt + 1'b1;

always @ ( posedge clk or negedge rst_n )
    if ( !rst_n )
        pulse <= 1'b0;
    else if ( clk_cnt == 9'd323 )
        pulse <= ~pulse;

assign  uart_clk16x = pulse;            
endmodule