top_uart.syr

uart的代码

-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 10    |
uart_clk_50m_inst/pulse1           | BUFG                   | 39    |
uart_tx_inst/tx_clk_cnt_31         | BUFG                   | 29    |
uart_rx_inst2/clkdiv_31            | BUFG                   | 20    |
uart_rx_inst1/clkdiv_31            | BUFG                   | 20    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.760ns (Maximum Frequency: 173.611MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.281ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.754ns (frequency: 173.792MHz)
  Total number of paths / destination ports: 124 / 11
-------------------------------------------------------------------------
Delay:               5.754ns (Levels of Logic = 3)
  Source:            uart_clk_50m_inst/clk_cnt_5 (FF)
  Destination:       uart_clk_50m_inst/clk_cnt_5 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: uart_clk_50m_inst/clk_cnt_5 to uart_clk_50m_inst/clk_cnt_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.720   1.260  uart_clk_50m_inst/clk_cnt_5 (uart_clk_50m_inst/clk_cnt_5)
     LUT4_D:I0->O          3   0.551   0.933  uart_clk_50m_inst/_n0000_SW1 (N413)
     LUT4:I3->O            4   0.551   0.985  uart_clk_50m_inst/_n0000 (uart_clk_50m_inst/_n0000)
     LUT3_L:I2->LO         1   0.551   0.000  uart_clk_50m_inst/clk_cnt_Eqn_51 (uart_clk_50m_inst/clk_cnt_Eqn_5)
     FDC:D                     0.203          uart_clk_50m_inst/clk_cnt_5
    ----------------------------------------
    Total                      5.754ns (2.576ns logic, 3.178ns route)
                                       (44.8% logic, 55.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'uart_clk_50m_inst/pulse1'
  Clock period: 5.760ns (frequency: 173.611MHz)
  Total number of paths / destination ports: 279 / 56
-------------------------------------------------------------------------
Delay:               5.760ns (Levels of Logic = 2)
  Source:            clk16x_cnt_7 (FF)
  Destination:       char_cnt_0 (FF)
  Source Clock:      uart_clk_50m_inst/pulse1 rising
  Destination Clock: uart_clk_50m_inst/pulse1 rising

  Data Path: clk16x_cnt_7 to char_cnt_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.720   1.216  clk16x_cnt_7 (clk16x_cnt_7)
     LUT4:I0->O            1   0.551   0.996  _n000117 (N115)
     LUT3:I1->O            9   0.551   1.124  _n000143 (_n0001)
     FDCE:CE                   0.602          char_cnt_0
    ----------------------------------------
    Total                      5.760ns (2.424ns logic, 3.336ns route)
                                       (42.1% logic, 57.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'uart_tx_inst/tx_clk_cnt_31'
  Clock period: 5.106ns (frequency: 195.848MHz)
  Total number of paths / destination ports: 249 / 28
-------------------------------------------------------------------------
Delay:               5.106ns (Levels of Logic = 3)
  Source:            uart_tx_inst/sent_bit_2 (FF)
  Destination:       uart_tx_inst/din_latch2_1 (FF)
  Source Clock:      uart_tx_inst/tx_clk_cnt_31 rising
  Destination Clock: uart_tx_inst/tx_clk_cnt_31 rising

  Data Path: uart_tx_inst/sent_bit_2 to uart_tx_inst/din_latch2_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              9   0.720   1.192  uart_tx_inst/sent_bit_2 (uart_tx_inst/sent_bit_2)
     LUT4:I2->O           11   0.551   1.212  uart_tx_inst/_n00491 (uart_tx_inst/N2)
     LUT3_L:I2->LO         1   0.551   0.126  uart_tx_inst/_n0048<1>1 (uart_tx_inst/_n0048<1>)
     LUT4_L:I3->LO         1   0.551   0.000  uart_tx_inst/_n0033111 (uart_tx_inst/_n0016<1>)
     FDC:D                     0.203          uart_tx_inst/din_latch2_1
    ----------------------------------------
    Total                      5.106ns (2.576ns logic, 2.530ns route)
                                       (50.5% logic, 49.5% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'uart_rx_inst2/clkdiv_31'
  Clock period: 4.361ns (frequency: 229.305MHz)
  Total number of paths / destination ports: 89 / 35
-------------------------------------------------------------------------
Delay:               4.361ns (Levels of Logic = 1)
  Source:            uart_rx_inst2/no_bits_rcvd_0 (FF)
  Destination:       uart_rx_inst2/rbr_0 (FF)
  Source Clock:      uart_rx_inst2/clkdiv_31 rising
  Destination Clock: uart_rx_inst2/clkdiv_31 rising

  Data Path: uart_rx_inst2/no_bits_rcvd_0 to uart_rx_inst2/rbr_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.720   1.405  uart_rx_inst2/no_bits_rcvd_0 (uart_rx_inst2/no_bits_rcvd_0)
     LUT4:I0->O            8   0.551   1.083  uart_rx_inst2/_n001611 (uart_rx_inst2/_n0016)
     FDCE:CE                   0.602          uart_rx_inst2/rbr_6
    ----------------------------------------
    Total                      4.361ns (1.873ns logic, 2.488ns route)
                                       (42.9% logic, 57.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'uart_rx_inst1/clkdiv_31'
  Clock period: 4.361ns (frequency: 229.305MHz)
  Total number of paths / destination ports: 89 / 35
-------------------------------------------------------------------------
Delay:               4.361ns (Levels of Logic = 1)
  Source:            uart_rx_inst1/no_bits_rcvd_0 (FF)
  Destination:       uart_rx_inst1/rbr_0 (FF)
  Source Clock:      uart_rx_inst1/clkdiv_31 rising
  Destination Clock: uart_rx_inst1/clkdiv_31 rising

  Data Path: uart_rx_inst1/no_bits_rcvd_0 to uart_rx_inst1/rbr_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              7   0.720   1.405  uart_rx_inst1/no_bits_rcvd_0 (uart_rx_inst1/no_bits_rcvd_0)
     LUT4:I0->O            8   0.551   1.083  uart_rx_inst1/_n001611 (uart_rx_inst1/_n0016)
     FDCE:CE                   0.602          uart_rx_inst1/rbr_6
    ----------------------------------------
    Total                      4.361ns (1.873ns logic, 2.488ns route)
                                       (42.9% logic, 57.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'uart_clk_50m_inst/pulse1'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              1.825ns (Levels of Logic = 1)
  Source:            rs232_r2 (PAD)
  Destination:       uart_rx_inst2/rxd1 (FF)
  Destination Clock: uart_clk_50m_inst/pulse1 rising

  Data Path: rs232_r2 to uart_rx_inst2/rxd1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   0.801  rs232_r2_IBUF (rs232_r2_IBUF)
     FDP:D                     0.203          uart_rx_inst2/rxd1
    ----------------------------------------
    Total                      1.825ns (1.024ns logic, 0.801ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'uart_tx_inst/tx_clk_cnt_31'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              7.281ns (Levels of Logic = 1)
  Source:            uart_tx_inst/txd (FF)
  Destination:       rs232_t1 (PAD)
  Source Clock:      uart_tx_inst/tx_clk_cnt_31 rising

  Data Path: uart_tx_inst/txd to rs232_t1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              4   0.720   0.917  uart_tx_inst/txd (uart_tx_inst/txd)
     OBUF:I->O                 5.644          rs232_t2_OBUF (rs232_t2)
    ----------------------------------------
    Total                      7.281ns (6.364ns logic, 0.917ns route)
                                       (87.4% logic, 12.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'uart_rx_inst1/clkdiv_31'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              7.165ns (Levels of Logic = 1)
  Source:            uart_rx_inst1/rbr_7 (FF)
  Destination:       rx1_data<7> (PAD)
  Source Clock:      uart_rx_inst1/clkdiv_31 rising

  Data Path: uart_rx_inst1/rbr_7 to rx1_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.720   0.801  uart_rx_inst1/rbr_7 (uart_rx_inst1/rbr_7)
     OBUF:I->O                 5.644          rx1_data_7_OBUF (rx1_data<7>)
    ----------------------------------------
    Total                      7.165ns (6.364ns logic, 0.801ns route)
                                       (88.8% logic, 11.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'uart_rx_inst2/clkdiv_31'
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Offset:              7.165ns (Levels of Logic = 1)
  Source:            uart_rx_inst2/rbr_7 (FF)
  Destination:       rx2_data<7> (PAD)
  Source Clock:      uart_rx_inst2/clkdiv_31 rising

  Data Path: uart_rx_inst2/rbr_7 to rx2_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.720   0.801  uart_rx_inst2/rbr_7 (uart_rx_inst2/rbr_7)
     OBUF:I->O                 5.644          rx2_data_7_OBUF (rx2_data<7>)
    ----------------------------------------
    Total                      7.165ns (6.364ns logic, 0.801ns route)
                                       (88.8% logic, 11.2% route)

=========================================================================
CPU : 16.33 / 16.86 s | Elapsed : 16.00 / 17.00 s
 
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Total memory usage is 128144 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   64 (   0 filtered)
Number of infos    :    0 (   0 filtered)