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📄 top_uart.syr

📁 uart的代码
💻 SYR
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    Related source file is "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/uart_clk_50m.v".    Found 9-bit up counter for signal <clk_cnt>.    Found 1-bit register for signal <pulse>.    Summary:	inferred   1 Counter(s).	inferred   1 D-type flip-flop(s).Unit <uart_clk_50m> synthesized.Synthesizing Unit <top_uart>.    Related source file is "F:/RHicdemo/sp3s_demo/pro104/rtl/verilog/top_uart.v".WARNING:Xst:646 - Signal <tbre> is assigned but never used.WARNING:Xst:646 - Signal <parity_error1> is assigned but never used.WARNING:Xst:646 - Signal <parity_error2> is assigned but never used.WARNING:Xst:646 - Signal <framing_error1> is assigned but never used.WARNING:Xst:646 - Signal <framing_error2> is assigned but never used.WARNING:Xst:646 - Signal <tsre> is assigned but never used.WARNING:Xst:646 - Signal <data_ready1> is assigned but never used.WARNING:Xst:646 - Signal <data_ready2> is assigned but never used.WARNING:Xst:1780 - Signal <dout1> is never used or assigned.WARNING:Xst:1780 - Signal <dout2> is never used or assigned.WARNING:Xst:646 - Signal <sdo> is assigned but never used.    Found 9-bit up counter for signal <char_cnt>.    Found 14-bit up counter for signal <clk16x_cnt>.    Summary:	inferred   2 Counter(s).Unit <top_uart> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs                                                 : 1 512x8-bit ROM                                         : 1# Adders/Subtractors                                   : 1 4-bit adder                                           : 1# Counters                                             : 10 14-bit up counter                                     : 1 4-bit up counter                                      : 7 9-bit up counter                                      : 2# Registers                                            : 56 1-bit register                                        : 50 4-bit register                                        : 1 8-bit register                                        : 5# Comparators                                          : 8 4-bit comparator greatequal                           : 4 4-bit comparator lessequal                            : 4# Multiplexers                                         : 23 1-bit 4-to-1 multiplexer                              : 20 4-bit 4-to-1 multiplexer                              : 1 8-bit 4-to-1 multiplexer                              : 2# Xors                                                 : 4 1-bit xor2                                            : 4==================================================================================================================================================*                       Advanced HDL Synthesis                          *=========================================================================WARNING:Xst:1291 - FF/Latch <data_ready> is unconnected in block <uart_rx_inst1>.WARNING:Xst:1291 - FF/Latch <framing_error> is unconnected in block <uart_rx_inst1>.WARNING:Xst:1291 - FF/Latch <parity_error> is unconnected in block <uart_rx_inst1>.WARNING:Xst:1291 - FF/Latch <parity> is unconnected in block <uart_rx_inst1>.WARNING:Xst:1291 - FF/Latch <data_ready> is unconnected in block <uart_rx_inst2>.WARNING:Xst:1291 - FF/Latch <framing_error> is unconnected in block <uart_rx_inst2>.WARNING:Xst:1291 - FF/Latch <parity_error> is unconnected in block <uart_rx_inst2>.WARNING:Xst:1291 - FF/Latch <parity> is unconnected in block <uart_rx_inst2>.WARNING:Xst:1291 - FF/Latch <tbre> is unconnected in block <uart_tx_inst>.WARNING:Xst:1291 - FF/Latch <sdo> is unconnected in block <uart_tx_inst>.WARNING:Xst:1291 - FF/Latch <tsre> is unconnected in block <uart_tx_inst>.=========================================================================Advanced HDL Synthesis ReportMacro Statistics# ROMs                                                 : 1 512x8-bit ROM                                         : 1# Adders/Subtractors                                   : 1 4-bit adder                                           : 1# Counters                                             : 10 14-bit up counter                                     : 1 4-bit up counter                                      : 7 9-bit up counter                                      : 2# Registers                                            : 71 Flip-Flops                                            : 71# Comparators                                          : 8 4-bit comparator greatequal                           : 4 4-bit comparator lessequal                            : 4# Multiplexers                                         : 23 1-bit 4-to-1 multiplexer                              : 20 4-bit 4-to-1 multiplexer                              : 1 8-bit 4-to-1 multiplexer                              : 2# Xors                                                 : 4 1-bit xor2                                            : 4==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Loading device for application Rf_Device from file '3s200.nph' in environment D:\Xilinx.WARNING:Xst:1291 - FF/Latch <clk16x_cnt_12> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <clk16x_cnt_13> is unconnected in block <top_uart>.Optimizing unit <top_uart> ...Optimizing unit <uart_tx> ...Optimizing unit <uart_rx> ...Mapping all equations...WARNING:Xst:1710 - FF/Latch  <uart_tx_inst/din_latch1_0> (without init value) has a constant value of 0 in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/wrn1> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbre> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/clk1x_enable> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_0> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_1> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_2> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_3> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_4> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_5> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_6> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tbr_7> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/wrn2> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/sdo> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsre> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_0> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_1> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_2> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_3> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_4> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_5> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_6> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/tsr_7> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/parity> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/no_bits_sent_0> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/no_bits_sent_1> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/no_bits_sent_2> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/no_bits_sent_3> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/clkdiv_0> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/clkdiv_1> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/clkdiv_2> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_tx_inst/clkdiv_3> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst2/data_ready> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst2/framing_error> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst2/parity_error> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst2/parity> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst1/data_ready> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst1/framing_error> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst1/parity_error> is unconnected in block <top_uart>.WARNING:Xst:1291 - FF/Latch <uart_rx_inst1/parity> is unconnected in block <top_uart>.Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block top_uart, actual ratio is 8.FlipFlop uart_tx_inst/sent_bit_0 has been replicated 3 time(s)FlipFlop uart_tx_inst/sent_bit_1 has been replicated 3 time(s)=========================================================================*                            Final Report                               *=========================================================================Final ResultsRTL Top Level Output File Name     : top_uart.ngrTop Level Output File Name         : top_uartOutput Format                      : NGCOptimization Goal                  : SpeedKeep Hierarchy                     : NODesign Statistics# IOs                              : 22Cell Usage :# BELS                             : 341#      GND                         : 1#      INV                         : 11#      LUT1                        : 1#      LUT1_L                      : 10#      LUT2                        : 14#      LUT2_D                      : 1#      LUT2_L                      : 4#      LUT3                        : 64#      LUT3_L                      : 15#      LUT4                        : 126#      LUT4_D                      : 7#      LUT4_L                      : 30#      MUXCY                       : 11#      MUXF5                       : 30#      MUXF6                       : 4#      VCC                         : 1#      XORCY                       : 11# FlipFlops/Latches                : 118#      FDC                         : 51#      FDCE                        : 59#      FDP                         : 8# Clock Buffers                    : 5#      BUFG                        : 4#      BUFGP                       : 1# IO Buffers                       : 21#      IBUF                        : 2#      IBUFG                       : 1#      OBUF                        : 18=========================================================================Device utilization summary:---------------------------Selected Device : 3s200pq208-4  Number of Slices:                     148  out of   1920     7%   Number of Slice Flip Flops:           118  out of   3840     3%   Number of 4 input LUTs:               272  out of   3840     7%   Number of bonded IOBs:                 22  out of    141    15%   Number of GCLKs:                        5  out of      8    62%  =========================================================================TIMING REPORTNOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT      GENERATED AFTER PLACE-and-ROUTE.Clock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |

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