sp3s_top.syr

uart的代码

WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rsr_7> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_0> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_3> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_4> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_5> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_6> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/rbr_7> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/parity> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/no_bits_rcvd_0> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/no_bits_rcvd_1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/no_bits_rcvd_2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/no_bits_rcvd_3> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/clkdiv_0> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/clkdiv_1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/clkdiv_2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_rx_inst1/clkdiv_3> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/wrn1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbre> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/clk1x_enable> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_0> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_3> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_4> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_5> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_6> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tbr_7> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/wrn2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/sdo> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsre> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_0> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_3> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_4> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_5> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_6> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/tsr_7> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/parity> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/no_bits_sent_0> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/no_bits_sent_1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/no_bits_sent_2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/no_bits_sent_3> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/clkdiv_0> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/clkdiv_1> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/clkdiv_2> is unconnected in block <sp3s_top>.
WARNING:Xst:1291 - FF/Latch <top_uart_inst/uart_tx_inst/clkdiv_3> is unconnected in block <sp3s_top>.
WARNING:Xst:1993 - Unrecognized value ibufg. Accepted values for attribute buffer_type on local signal <rst_n> are: BUFG, BUFR or NONE. Constraint is ignored.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sp3s_top, actual ratio is 7.
FlipFlop top_uart_inst/uart_tx_inst/sent_bit_0 has been replicated 3 time(s)
FlipFlop top_uart_inst/uart_tx_inst/sent_bit_1 has been replicated 3 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sp3s_top.ngr
Top Level Output File Name         : sp3s_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 136

Cell Usage :
# BELS                             : 313
#      GND                         : 1
#      INV                         : 7
#      LUT1                        : 1
#      LUT1_L                      : 10
#      LUT2                        : 6
#      LUT2_D                      : 1
#      LUT2_L                      : 4
#      LUT3                        : 58
#      LUT3_L                      : 15
#      LUT4                        : 116
#      LUT4_D                      : 7
#      LUT4_L                      : 30
#      MUXCY                       : 11
#      MUXF5                       : 30
#      MUXF6                       : 4
#      VCC                         : 1
#      XORCY                       : 11
# FlipFlops/Latches                : 64
#      FDC                         : 43
#      FDCE                        : 17
#      FDP                         : 4
# Clock Buffers                    : 3
#      BUFG                        : 2
#      BUFGP                       : 1
# IO Buffers                       : 8
#      IBUF                        : 1
#      OBUF                        : 7
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4 

 Number of Slices:                     134  out of   1920     6%  
 Number of Slice Flip Flops:            64  out of   3840     1%  
 Number of 4 input LUTs:               248  out of   3840     6%  
 Number of bonded IOBs:                  9  out of    141     6%  
 Number of GCLKs:                        3  out of      8    37%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
----------------------------------------+------------------------+-------+
Clock Signal                            | Clock buffer(FF name)  | Load  |
----------------------------------------+------------------------+-------+
clk                                     | BUFGP                  | 10    |
top_uart_inst/uart_clk_50m_inst/pulse1  | BUFG                   | 25    |
top_uart_inst/uart_tx_inst/tx_clk_cnt_31| BUFG                   | 29    |
----------------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 5.760ns (Maximum Frequency: 173.611MHz)
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: 7.281ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 5.754ns (frequency: 173.792MHz)
  Total number of paths / destination ports: 124 / 11
-------------------------------------------------------------------------
Delay:               5.754ns (Levels of Logic = 3)
  Source:            top_uart_inst/uart_clk_50m_inst/clk_cnt_5 (FF)
  Destination:       top_uart_inst/uart_clk_50m_inst/clk_cnt_5 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: top_uart_inst/uart_clk_50m_inst/clk_cnt_5 to top_uart_inst/uart_clk_50m_inst/clk_cnt_5
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              5   0.720   1.260  top_uart_inst/uart_clk_50m_inst/clk_cnt_5 (top_uart_inst/uart_clk_50m_inst/clk_cnt_5)
     LUT4_D:I0->O          3   0.551   0.933  top_uart_inst/uart_clk_50m_inst/_n0000_SW1 (N410)
     LUT4:I3->O            4   0.551   0.985  top_uart_inst/uart_clk_50m_inst/_n0000 (top_uart_inst/uart_clk_50m_inst/_n0000)
     LUT3_L:I2->LO         1   0.551   0.000  top_uart_inst/uart_clk_50m_inst/clk_cnt_Eqn_51 (top_uart_inst/uart_clk_50m_inst/clk_cnt_Eqn_5)
     FDC:D                     0.203          top_uart_inst/uart_clk_50m_inst/clk_cnt_5
    ----------------------------------------
    Total                      5.754ns (2.576ns logic, 3.178ns route)
                                       (44.8% logic, 55.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'top_uart_inst/uart_clk_50m_inst/pulse1'
  Clock period: 5.760ns (frequency: 173.611MHz)
  Total number of paths / destination ports: 241 / 34
-------------------------------------------------------------------------
Delay:               5.760ns (Levels of Logic = 2)
  Source:            top_uart_inst/clk16x_cnt_7 (FF)
  Destination:       top_uart_inst/char_cnt_0 (FF)
  Source Clock:      top_uart_inst/uart_clk_50m_inst/pulse1 rising
  Destination Clock: top_uart_inst/uart_clk_50m_inst/pulse1 rising

  Data Path: top_uart_inst/clk16x_cnt_7 to top_uart_inst/char_cnt_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              2   0.720   1.216  top_uart_inst/clk16x_cnt_7 (top_uart_inst/clk16x_cnt_7)
     LUT4:I0->O            1   0.551   0.996  top_uart_inst/_n000117 (top_uart_inst/_n0001_map182)
     LUT3:I1->O            9   0.551   1.124  top_uart_inst/_n000143 (top_uart_inst/_n0001)
     FDCE:CE                   0.602          top_uart_inst/char_cnt_0
    ----------------------------------------
    Total                      5.760ns (2.424ns logic, 3.336ns route)
                                       (42.1% logic, 57.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'top_uart_inst/uart_tx_inst/tx_clk_cnt_31'
  Clock period: 5.106ns (frequency: 195.848MHz)
  Total number of paths / destination ports: 249 / 28
-------------------------------------------------------------------------
Delay:               5.106ns (Levels of Logic = 3)
  Source:            top_uart_inst/uart_tx_inst/sent_bit_2 (FF)
  Destination:       top_uart_inst/uart_tx_inst/din_latch2_1 (FF)
  Source Clock:      top_uart_inst/uart_tx_inst/tx_clk_cnt_31 rising
  Destination Clock: top_uart_inst/uart_tx_inst/tx_clk_cnt_31 rising

  Data Path: top_uart_inst/uart_tx_inst/sent_bit_2 to top_uart_inst/uart_tx_inst/din_latch2_1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              9   0.720   1.192  top_uart_inst/uart_tx_inst/sent_bit_2 (top_uart_inst/uart_tx_inst/sent_bit_2)
     LUT4:I2->O           11   0.551   1.212  top_uart_inst/uart_tx_inst/_n00491 (top_uart_inst/uart_tx_inst/N2)
     LUT3_L:I2->LO         1   0.551   0.126  top_uart_inst/uart_tx_inst/_n0048<2>1 (top_uart_inst/uart_tx_inst/_n0048<2>)
     LUT4_L:I3->LO         1   0.551   0.000  top_uart_inst/uart_tx_inst/_n003321 (top_uart_inst/uart_tx_inst/_n0016<2>)
     FDC:D                     0.203          top_uart_inst/uart_tx_inst/din_latch2_2
    ----------------------------------------
    Total                      5.106ns (2.576ns logic, 2.530ns route)
                                       (50.5% logic, 49.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'top_uart_inst/uart_tx_inst/tx_clk_cnt_31'
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Offset:              7.281ns (Levels of Logic = 1)
  Source:            top_uart_inst/uart_tx_inst/txd (FF)
  Destination:       rs232_t1 (PAD)
  Source Clock:      top_uart_inst/uart_tx_inst/tx_clk_cnt_31 rising

  Data Path: top_uart_inst/uart_tx_inst/txd to rs232_t1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q              4   0.720   0.917  top_uart_inst/uart_tx_inst/txd (top_uart_inst/uart_tx_inst/txd)
     OBUF:I->O                 5.644          rs232_t2_OBUF (rs232_t2)
    ----------------------------------------
    Total                      7.281ns (6.364ns logic, 0.917ns route)
                                       (87.4% logic, 12.6% route)

=========================================================================
CPU : 18.77 / 19.41 s | Elapsed : 19.00 / 20.00 s
 
--> 

Total memory usage is 128144 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  213 (   0 filtered)
Number of infos    :    0 (   0 filtered)