armexio.fit.rpt

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Fitter report for armExIO compilation.
Mon Nov 24 10:25:12 2003
Version 3.0 Build 199 06/26/2003 SJ Full Version

Command: quartus_fit --import_settings_files=off --export_settings_files=off armExIO -c armExIO



---------------------
; Table of Contents ;
---------------------
   1. Legal Notice
   2. Flow Summary
   3. Flow Settings
   4. Flow Elapsed Time
   5. Fitter Summary
   6. Fitter Settings
   7. Fitter Device Options
   8. Fitter Equations
   9. Floorplan View
  10. Input Pins
  11. Output Pins
  12. Bidir Pins
  13. All Package Pins
  14. Control Signals
  15. Global & Other Fast Signals
  16. Carry Chains
  17. Cascade Chains
  18. Non-Global High Fan-Out Signals
  19. Peripheral Signals
  20. LAB
  21. Local Routing Interconnect
  22. LAB External Interconnect
  23. Row Interconnect
  24. LAB Column Interconnect
  25. EAB Column Interconnect
  26. Resource Usage Summary
  27. Fitter Resource Utilization by Entity
  28. Delay Chain Summary
  29. Pin-Out File
  30. Fitter Messages


----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



-----------------------------------------------------------------
; Flow Summary                                                  ;
-----------------------------------------------------------------
; Flow Status           ; Successful - Mon Nov 24 10:25:12 2003 ;
; Compiler Setting Name ; armExIO                               ;
; Top-level Entity Name ; armExIO                               ;
; Family                ; ACEX1K                                ;
; Device                ; EP1K50QC208-3                         ;
; Total logic elements  ; 275 / 2,880 ( 9 % )                   ;
; Total pins            ; 144 / 147 ( 97 % )                    ;
; Total memory bits     ; 0 / 40,960 ( 0 % )                    ;
; Total PLLs            ; 0 / 1 ( 0 % )                         ;
-----------------------------------------------------------------


-----------------------------------------------
; Flow Settings                               ;
-----------------------------------------------
; Option                ; Setting             ;
-----------------------------------------------
; Start date & time     ; 11/24/2003 10:24:54 ;
; Main task             ; Compilation         ;
; Compiler Setting Name ; armExIO             ;
-----------------------------------------------


---------------------------------------
; Flow Elapsed Time                   ;
---------------------------------------
; Module Name          ; Elapsed Time ;
---------------------------------------
; Analysis & Synthesis ; 00:00:04     ;
; Fitter               ; 00:00:13     ;
; Total                ; 00:00:17     ;
---------------------------------------


-----------------------------------------------------------------
; Fitter Summary                                                ;
-----------------------------------------------------------------
; Fitter Status         ; Successful - Mon Nov 24 10:25:12 2003 ;
; Compiler Setting Name ; armExIO                               ;
; Top-level Entity Name ; armExIO                               ;
; Family                ; ACEX1K                                ;
; Device                ; EP1K50QC208-3                         ;
; Total logic elements  ; 275 / 2,880 ( 9 % )                   ;
; Total pins            ; 144 / 147 ( 97 % )                    ;
; Total memory bits     ; 0 / 40,960 ( 0 % )                    ;
; Total PLLs            ; 0 / 1 ( 0 % )                         ;
-----------------------------------------------------------------


-------------------------------------------------------------------
; Fitter Settings                                                 ;
-------------------------------------------------------------------
; Option                                     ; Setting            ;
-------------------------------------------------------------------
; Device                                     ; EP1K50QC208-3      ;
; Fast Fit compilation                       ; Off                ;
; Optimize IOC register placement for timing ; On                 ;
; Optimize timing                            ; Normal Compilation ;
-------------------------------------------------------------------


---------------------------------------------------------------------------
; Fitter Device Options                                                   ;
---------------------------------------------------------------------------
; Option                                       ; Setting                  ;
---------------------------------------------------------------------------
; Auto-restart configuration after error       ; Off                      ;
; Release clears before tri-states             ; Off                      ;
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
---------------------------------------------------------------------------


---------------------
; Fitter Equations  ;
---------------------
The equations can be found in E:\Exp23_1\FPGA\rev_1\armExIO.fit.eqn.


-------------------
; Floorplan View  ;
-------------------
Floorplan report data cannot be output to ASCII.
Please use Quartus II to view the floorplan report data.


----------------------------------------------------------------------------------------------------------------------------------------------------------------
; Input Pins                                                                                                                                                   ;
----------------------------------------------------------------------------------------------------------------------------------------------------------------
; Name       ; Pin # ; Row ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; PCI I/O Enabled ; Single-Pin CE ; I/O Standard ;
----------------------------------------------------------------------------------------------------------------------------------------------------------------
; address[1] ; 195   ; --  ; 26   ; 37      ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; address[2] ; 193   ; --  ; 25   ; 37      ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; wr         ; 78    ; --  ; --   ; 8       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; cs         ; 125   ;  G  ; --   ; 9       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; address[0] ; 196   ; --  ; 27   ; 52      ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; address[4] ; 191   ; --  ; 23   ; 3       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;
; address[3] ; 192   ; --  ; 24   ; 3       ; no     ; no           ; no                      ; no            ; no              ; no            ; LVTTL/LVCMOS ;