armexio.map.qmsg

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· QMSG 代码 · 共 14 行

{  "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 24 10:24:53 2003 " "Info: Processing started: Mon Nov 24 10:24:53 2003" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off armExIO -c armExIO " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off armExIO -c armExIO" {  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf 6 6 " "Info: Found 6 design units and 6 entities in source file E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" { { "Info" "ISGN_ENTITY_NAME" "1 L2_2 " "Info: Found entity 1: L2_2" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "L2_2" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 197 11 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 L2_6 " "Info: Found entity 2: L2_6" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "L2_6" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 266 11 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 L2_8 " "Info: Found entity 3: L2_8" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "L2_8" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 173 11 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 L3_3C " "Info: Found entity 4: L3_3C" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "L3_3C" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 296 11 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 L3_78 " "Info: Found entity 5: L3_78" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "L3_78" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 226 11 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 armExIO " "Info: Found entity 6: armExIO" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "armExIO" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 331 11 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_latch " "Info: Found entity 1: lpm_latch" {  } { { "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" "lpm_latch" "" { Text "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" 39 1 0 } }  } 0}  } {  } 0 }
{  "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:\\quartus\\libraries\\others\\maxplus2\\21MUX.bdf 1 1 " "Info: Found 1 design units and 1 entities in source file c:\\quartus\\libraries\\others\\maxplus2\\21MUX.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 21MUX " "Info: Found entity 1: 21MUX" {  } { { "c:\\quartus\\libraries\\others\\maxplus2\\21MUX.bdf" "21MUX" "" { Schematic "c:\\quartus\\libraries\\others\\maxplus2\\21MUX.bdf" { { } } } }  } 0}  } {  } 0 }
{  "Info" "IRTL_INFERENCING_SUMMARY" "0 " "Info: Inferred 0 megafunctions from design logic" {  } {  } 0 }
{  "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "IOP1\[32\] GND " "Warning: Pin IOP1\[32\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 340 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP1\[33\] GND " "Warning: Pin IOP1\[33\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 340 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP1\[34\] GND " "Warning: Pin IOP1\[34\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 340 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP1\[35\] GND " "Warning: Pin IOP1\[35\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 340 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP1\[36\] GND " "Warning: Pin IOP1\[36\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 340 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP2\[32\] GND " "Warning: Pin IOP2\[32\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 341 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP2\[33\] GND " "Warning: Pin IOP2\[33\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 341 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP2\[34\] GND " "Warning: Pin IOP2\[34\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 341 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP2\[35\] GND " "Warning: Pin IOP2\[35\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 341 33 0 } }  } 0} { "Warning" "WMLS_MLS_STUCK_PIN" "IOP2\[36\] GND " "Warning: Pin IOP2\[36\] stuck at GND" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 341 33 0 } }  } 0}  } {  } 0 }
{  "Info" "IFTM_CARRY_SINGLE_TO_DOUBLE" "5 " "Info: Converted 5 single input CARRY primitives to CARRY_SUM primitives" {  } {  } 0 }
{  "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "11 " "Warning: Design contains 11 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "reset " "Warning: No output dependent on input pin reset" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 342 18 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "switch\[0\] " "Warning: No output dependent on input pin switch\[0\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 335 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "switch\[1\] " "Warning: No output dependent on input pin switch\[1\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 335 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "switch\[2\] " "Warning: No output dependent on input pin switch\[2\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 335 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "switch\[3\] " "Warning: No output dependent on input pin switch\[3\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 335 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "unused\[0\] " "Warning: No output dependent on input pin unused\[0\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 336 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "unused\[1\] " "Warning: No output dependent on input pin unused\[1\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 336 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "unused\[2\] " "Warning: No output dependent on input pin unused\[2\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 336 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "unused\[3\] " "Warning: No output dependent on input pin unused\[3\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 336 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "unused\[4\] " "Warning: No output dependent on input pin unused\[4\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 336 33 0 } }  } 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "unused\[5\] " "Warning: No output dependent on input pin unused\[5\]" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 336 33 0 } }  } 0}  } {  } 0 }
{  "Info" "ISCL_SCL_TM_SUMMARY" "414 " "Info: Implemented 414 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "25 " "Info: Implemented 25 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "103 " "Info: Implemented 103 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "16 " "Info: Implemented 16 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "270 " "Info: Implemented 270 logic cells" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 23 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 23 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 24 10:24:58 2003 " "Info: Processing ended: Mon Nov 24 10:24:58 2003" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0 }
{  "Info" "IQCU_REPORT_WRITTEN_TO" "armExIO.map.rpt " "Info: Writing report file armExIO.map.rpt" {  } {  } 0 }