armexio.csf.qmsg

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· QMSG 代码 · 共 37 行 · 第 1/5 页

QMSG
37 行
字号
12345
{  "Info" "ITDB_FULL_SLACK_RESULT" "mclk pin address\[7\] register led_cnt2_2_ 978.5 ns " "Info: Slack time is 978.5 ns for clock mclk between source pin address\[7\] and destination register led_cnt2_2_" { { "Info" "ITDB_FULL_TSU_REQUIREMENT" "999.900 ns + register " "Info: + tsu requirement for source pin and destination register is 999.900 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TSU_RESULT" "21.400 ns - " "Info: - tsu from clock to input pin is 21.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.200 ns + Longest pin register " "Info: + Longest pin to register delay is 24.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.700 ns) 3.700 ns address\[7\] 1 PIN Pin_187 " "Info: 1: + IC(0.000 ns) + CELL(3.700 ns) = 3.700 ns; Loc. = Pin_187; PIN Node = 'address\[7\]'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { address[7] } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 337 33 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.600 ns) 8.700 ns G_350_504 2 COMB LC3_F8 " "Info: 2: + IC(3.400 ns) + CELL(1.600 ns) = 8.700 ns; Loc. = LC3_F8; COMB Node = 'G_350_504'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "5.000 ns" { address[7] G_350_504 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1459 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 10.300 ns G_350_lc 3 COMB LC4_F8 " "Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 10.300 ns; Loc. = LC4_F8; COMB Node = 'G_350_lc'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.600 ns" { G_350_504 G_350_lc } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 950 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.900 ns) 12.400 ns G_356_lc~0 4 COMB LC2_F5 " "Info: 4: + IC(1.200 ns) + CELL(0.900 ns) = 12.400 ns; Loc. = LC2_F5; COMB Node = 'G_356_lc~0'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "2.100 ns" { G_350_lc G_356_lc~0 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 953 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 13.900 ns un1_wr_8_0_and2_0_and2~0 5 COMB LC3_F5 " "Info: 5: + IC(0.000 ns) + CELL(1.500 ns) = 13.900 ns; Loc. = LC3_F5; COMB Node = 'un1_wr_8_0_and2_0_and2~0'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.500 ns" { G_356_lc~0 un1_wr_8_0_and2_0_and2~0 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1708 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.500 ns) 17.500 ns lpm_latch:cnt4_1_\|latches\[0\]~1 6 COMB LC7_F19 " "Info: 6: + IC(2.100 ns) + CELL(1.500 ns) = 17.500 ns; Loc. = LC7_F19; COMB Node = 'lpm_latch:cnt4_1_\|latches\[0\]~1'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.600 ns" { un1_wr_8_0_and2_0_and2~0 lpm_latch:cnt4_1_|latches[0]~1 } "NODE_NAME" } } } { "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" "" "" { Text "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" 57 10 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(0.600 ns) 20.000 ns led_un1_cnt2_lt1_cry 7 COMB LC6_F5 " "Info: 7: + IC(1.900 ns) + CELL(0.600 ns) = 20.000 ns; Loc. = LC6_F5; COMB Node = 'led_un1_cnt2_lt1_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "2.500 ns" { lpm_latch:cnt4_1_|latches[0]~1 led_un1_cnt2_lt1_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1122 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 20.100 ns led_un1_cnt2_lt2_cry 8 COMB LC7_F5 " "Info: 8: + IC(0.000 ns) + CELL(0.100 ns) = 20.100 ns; Loc. = LC7_F5; COMB Node = 'led_un1_cnt2_lt2_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.100 ns" { led_un1_cnt2_lt1_cry led_un1_cnt2_lt2_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1129 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 20.200 ns led_un1_cnt2_lt3_cry 9 COMB LC8_F5 " "Info: 9: + IC(0.000 ns) + CELL(0.100 ns) = 20.200 ns; Loc. = LC8_F5; COMB Node = 'led_un1_cnt2_lt3_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.100 ns" { led_un1_cnt2_lt2_cry led_un1_cnt2_lt3_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1136 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.100 ns) 20.500 ns led_un1_cnt2_lt4_cry 10 COMB LC1_F7 " "Info: 10: + IC(0.200 ns) + CELL(0.100 ns) = 20.500 ns; Loc. = LC1_F7; COMB Node = 'led_un1_cnt2_lt4_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.300 ns" { led_un1_cnt2_lt3_cry led_un1_cnt2_lt4_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1143 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 20.600 ns led_un1_cnt2_lt5_cry 11 COMB LC2_F7 " "Info: 11: + IC(0.000 ns) + CELL(0.100 ns) = 20.600 ns; Loc. = LC2_F7; COMB Node = 'led_un1_cnt2_lt5_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.100 ns" { led_un1_cnt2_lt4_cry led_un1_cnt2_lt5_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1150 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 20.700 ns led_un1_cnt2_lt6_cry 12 COMB LC3_F7 " "Info: 12: + IC(0.000 ns) + CELL(0.100 ns) = 20.700 ns; Loc. = LC3_F7; COMB Node = 'led_un1_cnt2_lt6_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.100 ns" { led_un1_cnt2_lt5_cry led_un1_cnt2_lt6_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1157 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 22.000 ns led_un1_cnt2_lt7_cry 13 COMB LC4_F7 " "Info: 13: + IC(0.000 ns) + CELL(1.300 ns) = 22.000 ns; Loc. = LC4_F7; COMB Node = 'led_un1_cnt2_lt7_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { led_un1_cnt2_lt6_cry led_un1_cnt2_lt7_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 964 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.000 ns) 24.200 ns led_cnt2_2_ 14 REG LC3_F4 " "Info: 14: + IC(1.200 ns) + CELL(1.000 ns) = 24.200 ns; Loc. = LC3_F4; REG Node = 'led_cnt2_2_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "2.200 ns" { led_un1_cnt2_lt7_cry led_cnt2_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 357 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "14.000 ns " "Info: Total cell delay = 14.000 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.200 ns " "Info: Total interconnect delay = 10.200 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "24.200 ns" { address[7] address[7]~out G_350_504 G_350_lc G_356_lc~0 un1_wr_8_0_and2_0_and2~0 lpm_latch:cnt4_1_|latches[0]~1 led_un1_cnt2_lt1_cry led_un1_cnt2_lt2_cry led_un1_cnt2_lt3_cry led_un1_cnt2_lt4_cry led_un1_cnt2_lt5_cry led_un1_cnt2_lt6_cry led_un1_cnt2_lt7_cry led_cnt2_2_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 357 29 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 3.500 ns - Shortest register " "Info: - Shortest clock path from clock mclk to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns mclk 1 CLK Pin_183 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_183; CLK Node = 'mclk'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { mclk } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 343 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns led_cnt2_2_ 2 REG LC3_F4 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_F4; REG Node = 'led_cnt2_2_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { mclk led_cnt2_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 357 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns " "Info: Total cell delay = 2.200 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns " "Info: Total interconnect delay = 1.300 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt2_2_ } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "24.200 ns" { address[7] address[7]~out G_350_504 G_350_lc G_356_lc~0 un1_wr_8_0_and2_0_and2~0 lpm_latch:cnt4_1_|latches[0]~1 led_un1_cnt2_lt1_cry led_un1_cnt2_lt2_cry led_un1_cnt2_lt3_cry led_un1_cnt2_lt4_cry led_un1_cnt2_lt5_cry led_un1_cnt2_lt6_cry led_un1_cnt2_lt7_cry led_cnt2_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt2_2_ } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "24.200 ns" { address[7] address[7]~out G_350_504 G_350_lc G_356_lc~0 un1_wr_8_0_and2_0_and2~0 lpm_latch:cnt4_1_|latches[0]~1 led_un1_cnt2_lt1_cry led_un1_cnt2_lt2_cry led_un1_cnt2_lt3_cry led_un1_cnt2_lt4_cry led_un1_cnt2_lt5_cry led_un1_cnt2_lt6_cry led_un1_cnt2_lt7_cry led_cnt2_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt2_2_ } "NODE_NAME" } } }  } 0 }
{  "Info" "ITDB_FULL_SLACK_RESULT" "mclk register led_aaaa_0_ pin led\[0\] 989.3 ns " "Info: Slack time is 989.3 ns for clock mclk between source register led_aaaa_0_ and destination pin led\[0\]" { { "Info" "ITDB_FULL_TCO_REQUIREMENT" "999.900 ns + register " "Info: + tco requirement for source register and destination pin is 999.900 ns" {  } {  } 0} { "Info" "ITDB_SLACK_TCO_RESULT" "10.600 ns - " "Info: - tco from clock to output pin is 10.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 3.500 ns + Longest register " "Info: + Longest clock path from clock mclk to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns mclk 1 CLK Pin_183 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_183; CLK Node = 'mclk'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { mclk } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 343 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns led_aaaa_0_ 2 REG LC1_F3 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_F3; REG Node = 'led_aaaa_0_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { mclk led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 381 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns " "Info: Total cell delay = 2.200 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns " "Info: Total interconnect delay = 1.300 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_0_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 381 29 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.400 ns + Longest register pin " "Info: + Longest register to pin delay is 6.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_aaaa_0_ 1 REG LC1_F3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F3; REG Node = 'led_aaaa_0_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 381 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(4.600 ns) 6.400 ns led\[0\] 2 PIN Pin_136 " "Info: 2: + IC(1.800 ns) + CELL(4.600 ns) = 6.400 ns; Loc. = Pin_136; PIN Node = 'led\[0\]'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.400 ns" { led_aaaa_0_ led[0] } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 334 33 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns " "Info: Total cell delay = 4.600 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns " "Info: Total interconnect delay = 1.800 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.400 ns" { led_aaaa_0_ led[0] } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.400 ns" { led_aaaa_0_ led[0] } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.400 ns" { led_aaaa_0_ led[0] } "NODE_NAME" } } }  } 0 }
{  "Info" "ITDB_FULL_TPD_RESULT" "address\[7\] data\[4\] 38.200 ns Longest " "Info: Longest tpd from source pin address\[7\] to destination pin data\[4\] is 38.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.700 ns) 3.700 ns address\[7\] 1 PIN Pin_187 " "Info: 1: + IC(0.000 ns) + CELL(3.700 ns) = 3.700 ns; Loc. = Pin_187; PIN Node = 'address\[7\]'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { address[7] } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 337 33 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.600 ns) 8.700 ns G_350_504 2 COMB LC3_F8 " "Info: 2: + IC(3.400 ns) + CELL(1.600 ns) = 8.700 ns; Loc. = LC3_F8; COMB Node = 'G_350_504'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "5.000 ns" { address[7] G_350_504 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1459 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 10.300 ns G_350_lc 3 COMB LC4_F8 " "Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 10.300 ns; Loc. = LC4_F8; COMB Node = 'G_350_lc'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.600 ns" { G_350_504 G_350_lc } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 950 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 11.900 ns G_352 4 COMB LC2_F8 " "Info: 4: + IC(0.200 ns) + CELL(1.400 ns) = 11.900 ns; Loc. = LC2_F8; COMB Node = 'G_352'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.600 ns" { G_350_lc G_352 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1453 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 15.100 ns G_369 5 COMB LC2_F17 " "Info: 5: + IC(1.800 ns) + CELL(1.400 ns) = 15.100 ns; Loc. = LC2_F17; COMB Node = 'G_369'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.200 ns" { G_352 G_369 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1465 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.400 ns) 19.200 ns un1_wr_5_0_and2_0_and2 6 COMB LC6_H25 " "Info: 6: + IC(2.700 ns) + CELL(1.400 ns) = 19.200 ns; Loc. = LC6_H25; COMB Node = 'un1_wr_5_0_and2_0_and2'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "4.100 ns" { G_369 un1_wr_5_0_and2_0_and2 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1489 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(1.500 ns) 22.100 ns lpm_latch:iop2_20_\|q\[0\]~1 7 COMB LC1_H21 " "Info: 7: + IC(1.400 ns) + CELL(1.500 ns) = 22.100 ns; Loc. = LC1_H21; COMB Node = 'lpm_latch:iop2_20_\|q\[0\]~1'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "2.900 ns" { un1_wr_5_0_and2_0_and2 lpm_latch:iop2_20_|q[0]~1 } "NODE_NAME" } } } { "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" "" "" { Text "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(0.900 ns) 27.100 ns un1_iop1_6_0_i_0_and2_2_i_4_ 8 COMB LC2_F1 " "Info: 8: + IC(4.100 ns) + CELL(0.900 ns) = 27.100 ns; Loc. = LC2_F1; COMB Node = 'un1_iop1_6_0_i_0_and2_2_i_4_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "5.000 ns" { lpm_latch:iop2_20_|q[0]~1 un1_iop1_6_0_i_0_and2_2_i_4_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1519 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 28.100 ns un1_iop1_6_0_i_0_4_521_cand~9 9 COMB LC3_F1 " "Info: 9: + IC(0.000 ns) + CELL(1.000 ns) = 28.100 ns; Loc. = LC3_F1; COMB Node = 'un1_iop1_6_0_i_0_4_521_cand~9'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.000 ns" { un1_iop1_6_0_i_0_and2_2_i_4_ un1_iop1_6_0_i_0_4_521_cand~9 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1879 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 29.100 ns un1_iop1_6_0_i_0_4_524_cand~9 10 COMB LC4_F1 " "Info: 10: + IC(0.000 ns) + CELL(1.000 ns) = 29.100 ns; Loc. = LC4_F1; COMB Node = 'un1_iop1_6_0_i_0_4_524_cand~9'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.000 ns" { un1_iop1_6_0_i_0_4_521_cand~9 un1_iop1_6_0_i_0_4_524_cand~9 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1869 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 30.600 ns un1_iop1_6_0_i_0_4_~0 11 COMB LC5_F1 " "Info: 11: + IC(0.000 ns) + CELL(1.500 ns) = 30.600 ns; Loc. = LC5_F1; COMB Node = 'un1_iop1_6_0_i_0_4_~0'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.500 ns" { un1_iop1_6_0_i_0_4_524_cand~9 un1_iop1_6_0_i_0_4_~0 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1859 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 32.200 ns data\[4\]~3 12 COMB LC6_F1 " "Info: 12: + IC(0.200 ns) + CELL(1.400 ns) = 32.200 ns; Loc. = LC6_F1; COMB Node = 'data\[4\]~3'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.600 ns" { un1_iop1_6_0_i_0_4_~0 data[4]~3 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 338 33 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(4.900 ns) 38.200 ns data\[4\] 13 PIN Pin_103 " "Info: 13: + IC(1.100 ns) + CELL(4.900 ns) = 38.200 ns; Loc. = Pin_103; PIN Node = 'data\[4\]'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.000 ns" { data[4]~3 data[4] } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 338 33 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.100 ns " "Info: Total cell delay = 23.100 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.100 ns " "Info: Total interconnect delay = 15.100 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "38.200 ns" { address[7] address[7]~out G_350_504 G_350_lc G_352 G_369 un1_wr_5_0_and2_0_and2 lpm_latch:iop2_20_|q[0]~1 un1_iop1_6_0_i_0_and2_2_i_4_ un1_iop1_6_0_i_0_4_521_cand~9 un1_iop1_6_0_i_0_4_524_cand~9 un1_iop1_6_0_i_0_4_~0 data[4]~3 data[4] } "NODE_NAME" } } }  } 0 }
{  "Info" "ITDB_TH_RESULT" "led_cnt2_5_ wr mclk -6.600 ns register " "Info: th for register led_cnt2_5_ (data pin = wr, clock pin = mclk) is -6.600 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 3.500 ns + Longest register " "Info: + Longest clock path from clock mclk to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns mclk 1 CLK Pin_183 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_183; CLK Node = 'mclk'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { mclk } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 343 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns led_cnt2_5_ 2 REG LC8_F7 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC8_F7; REG Node = 'led_cnt2_5_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { mclk led_cnt2_5_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 366 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns " "Info: Total cell delay = 2.200 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns " "Info: Total interconnect delay = 1.300 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt2_5_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.800 ns + " "Info: + Micro hold delay of destination is 0.800 ns" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 366 29 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.900 ns - Shortest pin register " "Info: - Shortest pin to register delay is 10.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns wr 1 PIN Pin_78 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_78; PIN Node = 'wr'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { wr } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 344 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.400 ns) 5.400 ns un1_wr_8_0_and2_0_and2~0 2 COMB LC3_F5 " "Info: 2: + IC(1.800 ns) + CELL(1.400 ns) = 5.400 ns; Loc. = LC3_F5; COMB Node = 'un1_wr_8_0_and2_0_and2~0'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.200 ns" { wr un1_wr_8_0_and2_0_and2~0 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1708 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 7.100 ns lpm_latch:cnt4_3_\|latches\[0\]~1 3 COMB LC4_F5 " "Info: 3: + IC(0.200 ns) + CELL(1.500 ns) = 7.100 ns; Loc. = LC4_F5; COMB Node = 'lpm_latch:cnt4_3_\|latches\[0\]~1'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.700 ns" { un1_wr_8_0_and2_0_and2~0 lpm_latch:cnt4_3_|latches[0]~1 } "NODE_NAME" } } } { "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" "" "" { Text "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" 57 10 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.600 ns) 7.900 ns led_un1_cnt2_lt3_cry 4 COMB LC8_F5 " "Info: 4: + IC(0.200 ns) + CELL(0.600 ns) = 7.900 ns; Loc. = LC8_F5; COMB Node = 'led_un1_cnt2_lt3_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.800 ns" { lpm_latch:cnt4_3_|latches[0]~1 led_un1_cnt2_lt3_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1136 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.100 ns) 8.200 ns led_un1_cnt2_lt4_cry 5 COMB LC1_F7 " "Info: 5: + IC(0.200 ns) + CELL(0.100 ns) = 8.200 ns; Loc. = LC1_F7; COMB Node = 'led_un1_cnt2_lt4_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.300 ns" { led_un1_cnt2_lt3_cry led_un1_cnt2_lt4_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1143 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 8.300 ns led_un1_cnt2_lt5_cry 6 COMB LC2_F7 " "Info: 6: + IC(0.000 ns) + CELL(0.100 ns) = 8.300 ns; Loc. = LC2_F7; COMB Node = 'led_un1_cnt2_lt5_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.100 ns" { led_un1_cnt2_lt4_cry led_un1_cnt2_lt5_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1150 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 8.400 ns led_un1_cnt2_lt6_cry 7 COMB LC3_F7 " "Info: 7: + IC(0.000 ns) + CELL(0.100 ns) = 8.400 ns; Loc. = LC3_F7; COMB Node = 'led_un1_cnt2_lt6_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "0.100 ns" { led_un1_cnt2_lt5_cry led_un1_cnt2_lt6_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1157 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 9.700 ns led_un1_cnt2_lt7_cry 8 COMB LC4_F7 " "Info: 8: + IC(0.000 ns) + CELL(1.300 ns) = 9.700 ns; Loc. = LC4_F7; COMB Node = 'led_un1_cnt2_lt7_cry'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { led_un1_cnt2_lt6_cry led_un1_cnt2_lt7_cry } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 964 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 10.900 ns led_cnt2_5_ 9 REG LC8_F7 " "Info: 9: + IC(0.200 ns) + CELL(1.000 ns) = 10.900 ns; Loc. = LC8_F7; REG Node = 'led_cnt2_5_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.200 ns" { led_un1_cnt2_lt7_cry led_cnt2_5_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 366 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.300 ns " "Info: Total cell delay = 8.300 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns " "Info: Total interconnect delay = 2.600 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "10.900 ns" { wr wr~out un1_wr_8_0_and2_0_and2~0 lpm_latch:cnt4_3_|latches[0]~1 led_un1_cnt2_lt3_cry led_un1_cnt2_lt4_cry led_un1_cnt2_lt5_cry led_un1_cnt2_lt6_cry led_un1_cnt2_lt7_cry led_cnt2_5_ } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt2_5_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "10.900 ns" { wr wr~out un1_wr_8_0_and2_0_and2~0 lpm_latch:cnt4_3_|latches[0]~1 led_un1_cnt2_lt3_cry led_un1_cnt2_lt4_cry led_un1_cnt2_lt5_cry led_un1_cnt2_lt6_cry led_un1_cnt2_lt7_cry led_cnt2_5_ } "NODE_NAME" } } }  } 0 }
{  "Info" "ITDB_FULL_MIN_TCO_RESULT" "mclk led\[2\] led_aaaa_2_ 10.500 ns register " "Info: Minimum tco from clock mclk to destination pin led\[2\] through register led_aaaa_2_ is 10.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 3.500 ns + Shortest register " "Info: + Shortest clock path from clock mclk to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns mclk 1 CLK Pin_183 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_183; CLK Node = 'mclk'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { mclk } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 343 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns led_aaaa_2_ 2 REG LC1_F2 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_F2; REG Node = 'led_aaaa_2_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { mclk led_aaaa_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 387 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns " "Info: Total cell delay = 2.200 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns " "Info: Total interconnect delay = 1.300 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_2_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 387 29 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_aaaa_2_ 1 REG LC1_F2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F2; REG Node = 'led_aaaa_2_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { led_aaaa_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23
12345

armexio.csf.qmsg - 源码说明

本页面展示了「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全部源代码分别存放在各实验目录下面。」中的 armexio.csf.qmsg 源码文件，采用 QMSG 编程语言编写，共 37 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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