armexio.csf.qmsg

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· QMSG 代码 · 共 37 行 · 第 1/5 页

{  "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 24 10:25:13 2003 " "Info: Processing started: Mon Nov 24 10:25:13 2003" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --import_settings_files=off --export_settings_files=off armExIO -c armExIO " "Info: Command: quartus_asm --import_settings_files=off --export_settings_files=off armExIO -c armExIO" {  } {  } 0 }
{  "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 24 10:25:15 2003 " "Info: Processing ended: Mon Nov 24 10:25:15 2003" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0}  } {  } 0 }
{  "Info" "IQCU_REPORT_WRITTEN_TO" "armExIO.asm.rpt " "Info: Writing report file armExIO.asm.rpt" {  } {  } 0 }
{  "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 3.0 Build 199 06/26/2003 SJ Full Version " "Info: Version 3.0 Build 199 06/26/2003 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Nov 24 10:25:16 2003 " "Info: Processing started: Mon Nov 24 10:25:16 2003" {  } {  } 0}  } {  } 0 }
{  "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off armExIO -c armExIO " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off armExIO -c armExIO" {  } {  } 0 }
{  "Info" "ITDB_FULL_SLACK_RESULT" "mclk register led_cnt3_8_ register led_aaaa_0_ 988.0 ns " "Info: Slack time is 988.0 ns for clock mclk between source register led_cnt3_8_ and destination register led_aaaa_0_" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "83.33 MHz 12.0 ns " "Info: Fmax is 83.33 MHz (period = 12.0 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "998.600 ns + Largest register register " "Info: + Largest register to register requirement is 998.600 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "1000.000 ns + " "Info: + Setup relationship between source and destination is 1000.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 1500.000 ns " "Info: + Latch edge is 1500.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination mclk 1000.000 ns 500.000 ns , Inverted 50 " "Info: Clock period of Destination clock mclk is 1000.000 ns with , Inverted offset of 500.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 500.000 ns " "Info: - Launch edge is 500.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source mclk 1000.000 ns 500.000 ns , Inverted 50 " "Info: Clock period of Source clock mclk is 1000.000 ns with , Inverted offset of 500.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk destination 3.500 ns + Shortest register " "Info: + Shortest clock path from clock mclk to destination register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns mclk 1 CLK Pin_183 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_183; CLK Node = 'mclk'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { mclk } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 343 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns led_aaaa_0_ 2 REG LC1_F3 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_F3; REG Node = 'led_aaaa_0_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { mclk led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 381 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns " "Info: Total cell delay = 2.200 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns " "Info: Total interconnect delay = 1.300 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_0_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 3.500 ns - Longest register " "Info: - Longest clock path from clock mclk to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns mclk 1 CLK Pin_183 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_183; CLK Node = 'mclk'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { mclk } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 343 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns led_cnt3_8_ 2 REG LC1_F12 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_F12; REG Node = 'led_cnt3_8_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { mclk led_cnt3_8_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 414 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns " "Info: Total cell delay = 2.200 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns " "Info: Total interconnect delay = 1.300 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt3_8_ } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt3_8_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns - " "Info: - Micro clock to output delay of source is 0.700 ns" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 414 29 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns - " "Info: - Micro setup delay of destination is 0.700 ns" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 381 29 0 } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt3_8_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.600 ns - Longest register register " "Info: - Longest register to register delay is 10.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_cnt3_8_ 1 REG LC1_F12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F12; REG Node = 'led_cnt3_8_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { led_cnt3_8_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 414 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.500 ns) 2.700 ns G_28_0_or2_lut~23 2 COMB LC2_F10 " "Info: 2: + IC(1.200 ns) + CELL(1.500 ns) = 2.700 ns; Loc. = LC2_F10; COMB Node = 'G_28_0_or2_lut~23'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "2.700 ns" { led_cnt3_8_ G_28_0_or2_lut~23 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1675 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 4.300 ns G_28_0_or2_lut~19 3 COMB LC8_F10 " "Info: 3: + IC(0.200 ns) + CELL(1.400 ns) = 4.300 ns; Loc. = LC8_F10; COMB Node = 'G_28_0_or2_lut~19'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.600 ns" { G_28_0_or2_lut~23 G_28_0_or2_lut~19 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1675 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.400 ns) 6.900 ns G_28_0_or2~0 4 COMB LC7_F7 " "Info: 4: + IC(1.200 ns) + CELL(1.400 ns) = 6.900 ns; Loc. = LC7_F7; COMB Node = 'G_28_0_or2~0'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "2.600 ns" { G_28_0_or2_lut~19 G_28_0_or2~0 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1682 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 8.500 ns un1_cnt3_2_0 5 COMB LC5_F7 " "Info: 5: + IC(0.200 ns) + CELL(1.400 ns) = 8.500 ns; Loc. = LC5_F7; COMB Node = 'un1_cnt3_2_0'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.600 ns" { G_28_0_or2~0 un1_cnt3_2_0 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1380 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.900 ns) 10.600 ns led_aaaa_0_ 6 REG LC1_F3 " "Info: 6: + IC(1.200 ns) + CELL(0.900 ns) = 10.600 ns; Loc. = LC1_F3; REG Node = 'led_aaaa_0_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "2.100 ns" { un1_cnt3_2_0 led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 381 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.600 ns " "Info: Total cell delay = 6.600 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns " "Info: Total interconnect delay = 4.000 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "10.600 ns" { led_cnt3_8_ G_28_0_or2_lut~23 G_28_0_or2_lut~19 G_28_0_or2~0 un1_cnt3_2_0 led_aaaa_0_ } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_0_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_cnt3_8_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "10.600 ns" { led_cnt3_8_ G_28_0_or2_lut~23 G_28_0_or2_lut~19 G_28_0_or2~0 un1_cnt3_2_0 led_aaaa_0_ } "NODE_NAME" } } }  } 0 }