armexio.tan.qmsg

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· QMSG 代码 · 共 15 行 · 第 1/4 页

{  "Info" "ITDB_FULL_MIN_TCO_RESULT" "mclk led\[2\] led_aaaa_2_ 10.500 ns register " "Info: Minimum tco from clock mclk to destination pin led\[2\] through register led_aaaa_2_ is 10.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mclk source 3.500 ns + Shortest register " "Info: + Shortest clock path from clock mclk to source register is 3.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns mclk 1 CLK Pin_183 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_183; CLK Node = 'mclk'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { mclk } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 343 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(0.000 ns) 3.500 ns led_aaaa_2_ 2 REG LC1_F2 " "Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_F2; REG Node = 'led_aaaa_2_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.300 ns" { mclk led_aaaa_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 387 29 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns " "Info: Total cell delay = 2.200 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.300 ns " "Info: Total interconnect delay = 1.300 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_2_ } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.700 ns + " "Info: + Micro clock to output delay of source is 0.700 ns" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 387 29 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.300 ns + Shortest register pin " "Info: + Shortest register to pin delay is 6.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns led_aaaa_2_ 1 REG LC1_F2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F2; REG Node = 'led_aaaa_2_'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { led_aaaa_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 387 29 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(4.600 ns) 6.300 ns led\[2\] 2 PIN Pin_134 " "Info: 2: + IC(1.700 ns) + CELL(4.600 ns) = 6.300 ns; Loc. = Pin_134; PIN Node = 'led\[2\]'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.300 ns" { led_aaaa_2_ led[2] } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 334 33 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.600 ns " "Info: Total cell delay = 4.600 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.700 ns " "Info: Total interconnect delay = 1.700 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.300 ns" { led_aaaa_2_ led[2] } "NODE_NAME" } } }  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.500 ns" { mclk mclk~out led_aaaa_2_ } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "6.300 ns" { led_aaaa_2_ led[2] } "NODE_NAME" } } }  } 0 }
{  "Info" "ITDB_FULL_TPD_RESULT" "wr IOP1\[15\] 13.100 ns Shortest " "Info: Shortest tpd from source pin wr to destination pin IOP1\[15\] is 13.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.200 ns) 2.200 ns wr 1 PIN Pin_78 " "Info: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = Pin_78; PIN Node = 'wr'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "" { wr } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 344 18 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.500 ns) 5.500 ns un1_wr_3_0_and2_0_and2 2 COMB LC8_H25 " "Info: 2: + IC(1.800 ns) + CELL(1.500 ns) = 5.500 ns; Loc. = LC8_H25; COMB Node = 'un1_wr_3_0_and2_0_and2'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "3.300 ns" { wr un1_wr_3_0_and2_0_and2 } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 1495 21 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.500 ns) 7.200 ns lpm_latch:iop1_15_\|q\[0\]~1 3 COMB LC7_H25 " "Info: 3: + IC(0.200 ns) + CELL(1.500 ns) = 7.200 ns; Loc. = LC7_H25; COMB Node = 'lpm_latch:iop1_15_\|q\[0\]~1'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "1.700 ns" { un1_wr_3_0_and2_0_and2 lpm_latch:iop1_15_|q[0]~1 } "NODE_NAME" } } } { "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" "" "" { Text "c:\\quartus\\libraries\\megafunctions\\LPM_LATCH.tdf" 46 2 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(4.900 ns) 13.100 ns IOP1\[15\] 4 PIN Pin_65 " "Info: 4: + IC(1.000 ns) + CELL(4.900 ns) = 13.100 ns; Loc. = Pin_65; PIN Node = 'IOP1\[15\]'" {  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "5.900 ns" { lpm_latch:iop1_15_|q[0]~1 IOP1[15] } "NODE_NAME" } } } { "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" "" "" { Text "E:\\Exp23_1\\FPGA\\rev_1\\armExIO.edf" 340 33 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "10.100 ns " "Info: Total cell delay = 10.100 ns" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.000 ns " "Info: Total interconnect delay = 3.000 ns" {  } {  } 0}  } { { "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" "" "" { Report "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO_cmp.qrpt" Compiler "armExIO" "UNKNOWN" "V1" "E:\\Exp23_1\\FPGA\\rev_1\\db\\armExIO.quartus_db" { Floorplan "" "" "13.100 ns" { wr wr~out un1_wr_3_0_and2_0_and2 lpm_latch:iop1_15_|q[0]~1 IOP1[15] } "NODE_NAME" } } }  } 0 }
{  "Info" "ITAN_REQUIREMENTS_MET" "" "Info: All timing requirements were met. See Report window for more details." {  } {  } 0 }
{  "Warning" "WTAN_INVALID_ASSIGNMENTS_FOUND" "" "Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details" {  } {  } 0 }