armexio_hier_info

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· 代码 · 共 1,605 行 · 第 1/3 页

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1,605 行
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123

|armExIO|LPM_LATCH:iop1_24_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_25_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_26_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_27_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_28_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_29_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_3_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_30_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_31_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_4_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_5_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_6_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_7_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_8_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_9_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_0_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_1_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_10_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_11_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_12_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_13_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_14_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_15_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_16_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_17_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_18_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_19_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_2_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_20_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_21_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_22_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_23_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_24_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_25_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_26_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_27_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_28_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_29_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_3_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_30_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_31_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_4_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_5_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_6_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop2_7_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
123

armexio_hier_info - 源码说明

本页面展示了「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全部源代码分别存放在各实验目录下面。」中的 armexio_hier_info 源码文件，采用 编程语言编写，共 1,605 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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