armexio_hier_info

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· 代码 · 共 1,605 行 · 第 1/3 页

|armExIO
address[0] => un1_iop1_6_0_i_0_7_526_lut.DATAB
address[0] => un1_iop1_6_0_i_0_7_529_lut.DATAC
address[0] => un1_iop1_6_0_i_0_lut_7_.DATAC
address[0] => un1_iop1_6_0_i_0_6_531_lut.DATAB
address[0] => un1_iop1_6_0_i_0_6_534_lut.DATAC
address[0] => un1_iop1_6_0_i_0_lut_6_.DATAC
address[0] => un1_iop1_6_0_i_0_5_516_lut.DATAB
address[0] => un1_iop1_6_0_i_0_5_519_lut.DATAC
address[0] => un1_iop1_6_0_i_0_lut_5_.DATAC
address[0] => un1_iop1_6_0_i_0_4_521_lut.DATAB
address[0] => un1_iop1_6_0_i_0_4_524_lut.DATAC
address[0] => un1_iop1_6_0_i_0_lut_4_.DATAC
address[0] => un1_iop1_6_0_i_0_3_546_lut.DATAB
address[0] => un1_iop1_6_0_i_0_3_549_lut.DATAC
address[0] => un1_iop1_6_0_i_0_lut_3_.DATAC
address[0] => un1_iop1_6_0_i_0_2_551_lut.DATAB
address[0] => un1_iop1_6_0_i_0_2_554_lut.DATAC
address[0] => un1_iop1_6_0_i_0_lut_2_.DATAC
address[0] => un1_iop1_6_0_i_0_1_536_lut.DATAB
address[0] => un1_iop1_6_0_i_0_1_539_lut.DATAC
address[0] => un1_iop1_6_0_i_0_lut_1_.DATAC
address[0] => un1_iop1_6_0_i_0_0_543_lut.DATAB
address[0] => un1_iop1_6_0_0_0_8_571_lut.DATAB
address[0] => un1_wr_1_0_and2_0_and2_lut.DATAD
address[0] => un1_iop1_6_0_i_0_0_540.DATAC
address[0] => un1_iop1_6_0_0_0_9_569.DATAC
address[0] => un1_iop1_6_0_0_0_9_568.DATAC
address[0] => un1_iop1_6_0_0_0_8_573.DATAC
address[0] => un1_iop1_6_0_0_0_8_572.DATAC
address[0] => un1_wr_6_0_and2_0_and2.DATAA
address[0] => un1_iop1_6_0_0_0_and2_1_i_8_.DATAB
address[0] => un1_iop1_6_0_0_0_and2_1_9_.DATAB
address[0] => un1_iop1_6_0_0_0_and2_2_9_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_0_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_3_0_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_1_1_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_i_1_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_1_2_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_i_2_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_1_3_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_i_3_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_1_4_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_i_4_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_1_5_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_i_5_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_1_6_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_i_6_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_1_7_.DATAB
address[0] => un1_iop1_6_0_i_0_and2_2_i_7_.DATAB
address[0] => G_368.DATAB
address[0] => G_369.DATAB
address[0] => G_356.DATAB
address[1] => un1_iop1_6_0_i_0_7_526_lut.DATAD
address[1] => un1_iop1_6_0_i_0_6_531_lut.DATAD
address[1] => un1_iop1_6_0_i_0_5_516_lut.DATAD
address[1] => un1_iop1_6_0_i_0_4_521_lut.DATAD
address[1] => un1_iop1_6_0_i_0_3_546_lut.DATAD
address[1] => un1_iop1_6_0_i_0_2_551_lut.DATAD
address[1] => un1_iop1_6_0_i_0_1_536_lut.DATAD
address[1] => un1_iop1_6_0_0_0_8_571_lut.DATAD
address[1] => un1_wr_6_0_and2_0_and2_508_lut.DATAB
address[1] => un1_wr_8_0_and2_0_and2_lut.DATAD
address[1] => un1_iop1_6_0_i_0_7_527.DATAD
address[1] => un1_iop1_6_0_i_0_6_532.DATAD
address[1] => un1_iop1_6_0_i_0_5_517.DATAD
address[1] => un1_iop1_6_0_i_0_4_522.DATAD
address[1] => un1_iop1_6_0_i_0_3_547.DATAD
address[1] => un1_iop1_6_0_i_0_2_552.DATAD
address[1] => un1_iop1_6_0_i_0_1_537.DATAD
address[1] => un1_iop1_6_0_0_0_and2_1_i_8_.DATAD
address[1] => un1_iop1_6_0_0_0_and2_1_9_.DATAD
address[1] => un1_iop1_6_0_0_0_and2_2_9_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_i_0_.DATAC
address[1] => un1_iop1_6_0_i_0_and2_2_0_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_3_0_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_2_i_1_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_2_i_2_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_2_i_3_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_2_i_4_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_2_i_5_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_2_i_6_.DATAD
address[1] => un1_iop1_6_0_i_0_and2_2_i_7_.DATAD
address[1] => G_355.DATAB
address[1] => G_366.DATAC
address[1] => G_353.DATAA
address[1] => G_369.DATAD
address[1] => un1_un30_rd_0_and2_0_1_512.DATAC
address[2] => un1_iop1_6_0_i_0_7_526_lut.DATAC
address[2] => un1_iop1_6_0_i_0_6_531_lut.DATAC
address[2] => un1_iop1_6_0_i_0_5_516_lut.DATAC
address[2] => un1_iop1_6_0_i_0_4_521_lut.DATAC
address[2] => un1_iop1_6_0_i_0_3_546_lut.DATAC
address[2] => un1_iop1_6_0_i_0_2_551_lut.DATAC
address[2] => un1_iop1_6_0_i_0_1_536_lut.DATAC
address[2] => un1_iop1_6_0_0_0_8_571_lut.DATAC
address[2] => un1_wr_6_0_and2_0_and2_508_lut.DATAA
address[2] => un1_wr_8_0_and2_0_and2_lut.DATAC
address[2] => un1_iop1_6_0_i_0_7_527.DATAC
address[2] => un1_iop1_6_0_i_0_6_532.DATAC
address[2] => un1_iop1_6_0_i_0_5_517.DATAC
address[2] => un1_iop1_6_0_i_0_4_522.DATAC
address[2] => un1_iop1_6_0_i_0_3_547.DATAC
address[2] => un1_iop1_6_0_i_0_2_552.DATAC
address[2] => un1_iop1_6_0_i_0_1_537.DATAC
address[2] => un1_iop1_6_0_0_0_and2_1_i_8_.DATAC
address[2] => un1_iop1_6_0_0_0_and2_1_9_.DATAC
address[2] => un1_iop1_6_0_0_0_and2_2_9_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_i_0_.DATAB
address[2] => un1_iop1_6_0_i_0_and2_2_0_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_3_0_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_2_i_1_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_2_i_2_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_2_i_3_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_2_i_4_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_2_i_5_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_2_i_6_.DATAC
address[2] => un1_iop1_6_0_i_0_and2_2_i_7_.DATAC
address[2] => G_355.DATAA
address[2] => G_366.DATAB
address[2] => G_353.DATAB
address[2] => G_369.DATAC
address[2] => un1_un30_rd_0_and2_0_1_512.DATAB
address[3] => un1_wr_6_0_and2_0_and2_508_lut.DATAD
address[3] => G_352.DATAC
address[4] => un1_wr_6_0_and2_0_and2_508_lut.DATAC
address[4] => G_352.DATAB
address[5] => G_350_504.DATAA
address[6] => G_350.DATAB
address[7] => G_350_504.DATAD
address[8] => G_350_504.DATAC
address[9] => G_350_504.DATAB
cs => un1_wr_8_0_and2_0_and2_lut.DATAB
cs => un1_wr_1_0_and2_0_and2_lut.DATAB
cs => un1_wr_6_0_and2_0_and2.DATAD
cs => un1_wr_2_0_and2_0_and2.DATAC
cs => un1_wr_3_0_and2_0_and2.DATAC
cs => un1_wr_4_0_and2_0_and2.DATAC
cs => un1_wr_5_0_and2_0_and2.DATAC
cs => un1_wr_7_0_and2_0_and2.DATAC
cs => un1_un30_rd_0_and2_0_15_.DATAD
data[0] <= data_11_0_
data[1] <= data_11_1_
data[2] <= data_11_2_
data[3] <= data_11_3_
data[4] <= data_11_4_
data[5] <= data_11_5_
data[6] <= data_11_6_
data[7] <= data_11_7_
data[8] <= data_11_8_
data[9] <= data_11_9_
data[10] <= data_11_10_
data[11] <= data_11_11_
data[12] <= data_11_12_
data[13] <= data_11_13_
data[14] <= data_11_14_
data[15] <= data_11_15_
IOP1[0] <= LPM_LATCH:iop1_0_.Q0
IOP1[1] <= LPM_LATCH:iop1_1_.Q0
IOP1[2] <= LPM_LATCH:iop1_2_.Q0
IOP1[3] <= LPM_LATCH:iop1_3_.Q0
IOP1[4] <= LPM_LATCH:iop1_4_.Q0
IOP1[5] <= LPM_LATCH:iop1_5_.Q0
IOP1[6] <= LPM_LATCH:iop1_6_.Q0
IOP1[7] <= LPM_LATCH:iop1_7_.Q0
IOP1[8] <= LPM_LATCH:iop1_8_.Q0
IOP1[9] <= LPM_LATCH:iop1_9_.Q0
IOP1[10] <= LPM_LATCH:iop1_10_.Q0
IOP1[11] <= LPM_LATCH:iop1_11_.Q0
IOP1[12] <= LPM_LATCH:iop1_12_.Q0
IOP1[13] <= LPM_LATCH:iop1_13_.Q0
IOP1[14] <= LPM_LATCH:iop1_14_.Q0
IOP1[15] <= LPM_LATCH:iop1_15_.Q0
IOP1[16] <= LPM_LATCH:iop1_16_.Q0
IOP1[17] <= LPM_LATCH:iop1_17_.Q0
IOP1[18] <= LPM_LATCH:iop1_18_.Q0
IOP1[19] <= LPM_LATCH:iop1_19_.Q0
IOP1[20] <= LPM_LATCH:iop1_20_.Q0
IOP1[21] <= LPM_LATCH:iop1_21_.Q0
IOP1[22] <= LPM_LATCH:iop1_22_.Q0
IOP1[23] <= LPM_LATCH:iop1_23_.Q0
IOP1[24] <= LPM_LATCH:iop1_24_.Q0
IOP1[25] <= LPM_LATCH:iop1_25_.Q0
IOP1[26] <= LPM_LATCH:iop1_26_.Q0
IOP1[27] <= LPM_LATCH:iop1_27_.Q0
IOP1[28] <= LPM_LATCH:iop1_28_.Q0
IOP1[29] <= LPM_LATCH:iop1_29_.Q0
IOP1[30] <= LPM_LATCH:iop1_30_.Q0
IOP1[31] <= LPM_LATCH:iop1_31_.Q0
IOP1[32] <= IOP1_buf_32_.DB_MAX_OUTPUT_PORT_TYPE
IOP1[33] <= IOP1_buf_33_.DB_MAX_OUTPUT_PORT_TYPE
IOP1[34] <= IOP1_buf_34_.DB_MAX_OUTPUT_PORT_TYPE
IOP1[35] <= IOP1_buf_35_.DB_MAX_OUTPUT_PORT_TYPE
IOP1[36] <= IOP1_buf_36_.DB_MAX_OUTPUT_PORT_TYPE
IOP2[0] <= LPM_LATCH:iop2_0_.Q0
IOP2[1] <= LPM_LATCH:iop2_1_.Q0
IOP2[2] <= LPM_LATCH:iop2_2_.Q0
IOP2[3] <= LPM_LATCH:iop2_3_.Q0
IOP2[4] <= LPM_LATCH:iop2_4_.Q0
IOP2[5] <= LPM_LATCH:iop2_5_.Q0
IOP2[6] <= LPM_LATCH:iop2_6_.Q0
IOP2[7] <= LPM_LATCH:iop2_7_.Q0
IOP2[8] <= LPM_LATCH:iop2_8_.Q0
IOP2[9] <= LPM_LATCH:iop2_9_.Q0
IOP2[10] <= LPM_LATCH:iop2_10_.Q0
IOP2[11] <= LPM_LATCH:iop2_11_.Q0
IOP2[12] <= LPM_LATCH:iop2_12_.Q0
IOP2[13] <= LPM_LATCH:iop2_13_.Q0
IOP2[14] <= LPM_LATCH:iop2_14_.Q0
IOP2[15] <= LPM_LATCH:iop2_15_.Q0
IOP2[16] <= LPM_LATCH:iop2_16_.Q0
IOP2[17] <= LPM_LATCH:iop2_17_.Q0
IOP2[18] <= LPM_LATCH:iop2_18_.Q0
IOP2[19] <= LPM_LATCH:iop2_19_.Q0
IOP2[20] <= LPM_LATCH:iop2_20_.Q0
IOP2[21] <= LPM_LATCH:iop2_21_.Q0
IOP2[22] <= LPM_LATCH:iop2_22_.Q0
IOP2[23] <= LPM_LATCH:iop2_23_.Q0
IOP2[24] <= LPM_LATCH:iop2_24_.Q0
IOP2[25] <= LPM_LATCH:iop2_25_.Q0
IOP2[26] <= LPM_LATCH:iop2_26_.Q0
IOP2[27] <= LPM_LATCH:iop2_27_.Q0
IOP2[28] <= LPM_LATCH:iop2_28_.Q0
IOP2[29] <= LPM_LATCH:iop2_29_.Q0
IOP2[30] <= LPM_LATCH:iop2_30_.Q0
IOP2[31] <= LPM_LATCH:iop2_31_.Q0
IOP2[32] <= IOP2_buf_32_.DB_MAX_OUTPUT_PORT_TYPE
IOP2[33] <= IOP2_buf_33_.DB_MAX_OUTPUT_PORT_TYPE
IOP2[34] <= IOP2_buf_34_.DB_MAX_OUTPUT_PORT_TYPE
IOP2[35] <= IOP2_buf_35_.DB_MAX_OUTPUT_PORT_TYPE
IOP2[36] <= IOP2_buf_36_.DB_MAX_OUTPUT_PORT_TYPE
IOP3[0] <= LPM_LATCH:iop3_0_.Q0
IOP3[1] <= LPM_LATCH:iop3_1_.Q0
IOP3[2] <= LPM_LATCH:iop3_2_.Q0
IOP3[3] <= LPM_LATCH:iop3_3_.Q0
IOP3[4] <= LPM_LATCH:iop3_4_.Q0
IOP3[5] <= LPM_LATCH:iop3_5_.Q0
IOP3[6] <= LPM_LATCH:iop3_6_.Q0
IOP3[7] <= LPM_LATCH:iop3_7_.Q0
IOP3[8] <= LPM_LATCH:iop3_8_.Q0
IOP3[9] <= LPM_LATCH:iop3_9_.Q0
IOP3[10] <= LPM_LATCH:iop3_10_.Q0
IOP3[11] <= LPM_LATCH:iop3_11_.Q0
IOP3[12] <= LPM_LATCH:iop3_12_.Q0
IOP3[13] <= LPM_LATCH:iop3_13_.Q0
IOP3[14] <= LPM_LATCH:iop3_14_.Q0
IOP3[15] <= LPM_LATCH:iop3_15_.Q0
IOP3[16] <= LPM_LATCH:iop3_16_.Q0
IOP3[17] <= LPM_LATCH:iop3_17_.Q0
IOP3[18] <= LPM_LATCH:iop3_18_.Q0
IOP3[19] <= LPM_LATCH:iop3_19_.Q0
IOP3[20] <= LPM_LATCH:iop3_20_.Q0
IOP3[21] <= LPM_LATCH:iop3_21_.Q0
IOP3[22] <= LPM_LATCH:iop3_22_.Q0
IOP3[23] <= LPM_LATCH:iop3_23_.Q0
IOP3[24] <= LPM_LATCH:iop3_24_.Q0
IOP3[25] <= LPM_LATCH:iop3_25_.Q0
led[0] <= led_aaaa_0_.DB_MAX_OUTPUT_PORT_TYPE
led[1] <= led_aaaa_1_.DB_MAX_OUTPUT_PORT_TYPE
led[2] <= led_aaaa_2_.DB_MAX_OUTPUT_PORT_TYPE
mclk => mclk_i.IN0
rd => un1_un30_rd_0_and2_0_15_.DATAC
wr => un1_wr_8_0_and2_0_and2_lut.DATAA
wr => un1_wr_1_0_and2_0_and2_lut.DATAA
wr => un1_wr_6_0_and2_0_and2.DATAC
wr => un1_wr_2_0_and2_0_and2.DATAB
wr => un1_wr_3_0_and2_0_and2.DATAB
wr => un1_wr_4_0_and2_0_and2.DATAB
wr => un1_wr_5_0_and2_0_and2.DATAB
wr => un1_wr_7_0_and2_0_and2.DATAB


|armExIO|L2_2:cnt3_3_0_and2_L_18_
I0 => G_2.IN1
I1 => G_1.IN0
Z <= G_2.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|L2_2:cnt3_3_0_and2_L_19_
I0 => G_2.IN1
I1 => G_1.IN0
Z <= G_2.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_0_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_1_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_2_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_3_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_4_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_5_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_6_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:cnt4_7_
data[0] => latches[0].DATAIN
gate => latches[0].LATCH_ENABLE
q[0] <= latches[0].DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_0_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_1_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_10_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_11_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_12_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_13_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_14_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_15_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_16_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_17_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_18_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_19_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_2_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_20_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_21_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_22_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE


|armExIO|LPM_LATCH:iop1_23_
data[0] => clrn[0]~1.IN1
data[0] => altr_temp~4.IN0
gate => altr_temp~0.IN0
gate => altr_temp~3.IN0
aclr => clrn[0]~0.IN0
aclr => prn[0].IN0
aset => altr_temp~1.IN0
aset => altr_temp~2.IN0
q[0] <= q[0]~0.DB_MAX_OUTPUT_PORT_TYPE