armexio.esf

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· ESF 代码 · 共 169 行

TIMING_REQUIREMENTS
{
	led[0] : TCO_REQUIREMENT = 999.9ns;
	led[1] : TCO_REQUIREMENT = 999.9ns;
	led[2] : TCO_REQUIREMENT = 999.9ns;
	data[0] : TCO_REQUIREMENT = 999.9ns;
	data[1] : TCO_REQUIREMENT = 999.9ns;
	data[2] : TCO_REQUIREMENT = 999.9ns;
	data[3] : TCO_REQUIREMENT = 999.9ns;
	data[4] : TCO_REQUIREMENT = 999.9ns;
	data[5] : TCO_REQUIREMENT = 999.9ns;
	data[6] : TCO_REQUIREMENT = 999.9ns;
	data[7] : TCO_REQUIREMENT = 999.9ns;
	data[8] : TCO_REQUIREMENT = 999.9ns;
	data[9] : TCO_REQUIREMENT = 999.9ns;
	data[10] : TCO_REQUIREMENT = 999.9ns;
	data[11] : TCO_REQUIREMENT = 999.9ns;
	data[12] : TCO_REQUIREMENT = 999.9ns;
	data[13] : TCO_REQUIREMENT = 999.9ns;
	data[14] : TCO_REQUIREMENT = 999.9ns;
	data[15] : TCO_REQUIREMENT = 999.9ns;
	IOP[30] : TCO_REQUIREMENT = 999.9ns;
	IOP[31] : TCO_REQUIREMENT = 999.9ns;
	IOP[32] : TCO_REQUIREMENT = 999.9ns;
	IOP[33] : TCO_REQUIREMENT = 999.9ns;
	IOP[34] : TCO_REQUIREMENT = 999.9ns;
	IOP[35] : TCO_REQUIREMENT = 999.9ns;
	IOP[36] : TCO_REQUIREMENT = 999.9ns;
	IOP[37] : TCO_REQUIREMENT = 999.9ns;
	IOP[38] : TCO_REQUIREMENT = 999.9ns;
	IOP[39] : TCO_REQUIREMENT = 999.9ns;
	IOP[310] : TCO_REQUIREMENT = 999.9ns;
	IOP[311] : TCO_REQUIREMENT = 999.9ns;
	IOP[312] : TCO_REQUIREMENT = 999.9ns;
	IOP[313] : TCO_REQUIREMENT = 999.9ns;
	IOP[314] : TCO_REQUIREMENT = 999.9ns;
	IOP[315] : TCO_REQUIREMENT = 999.9ns;
	IOP[316] : TCO_REQUIREMENT = 999.9ns;
	IOP[317] : TCO_REQUIREMENT = 999.9ns;
	IOP[318] : TCO_REQUIREMENT = 999.9ns;
	IOP[319] : TCO_REQUIREMENT = 999.9ns;
	IOP[320] : TCO_REQUIREMENT = 999.9ns;
	IOP[321] : TCO_REQUIREMENT = 999.9ns;
	IOP[322] : TCO_REQUIREMENT = 999.9ns;
	IOP[323] : TCO_REQUIREMENT = 999.9ns;
	IOP[324] : TCO_REQUIREMENT = 999.9ns;
	IOP[325] : TCO_REQUIREMENT = 999.9ns;
	IOP[10] : TCO_REQUIREMENT = 999.9ns;
	IOP[11] : TCO_REQUIREMENT = 999.9ns;
	IOP[12] : TCO_REQUIREMENT = 999.9ns;
	IOP[13] : TCO_REQUIREMENT = 999.9ns;
	IOP[14] : TCO_REQUIREMENT = 999.9ns;
	IOP[15] : TCO_REQUIREMENT = 999.9ns;
	IOP[16] : TCO_REQUIREMENT = 999.9ns;
	IOP[17] : TCO_REQUIREMENT = 999.9ns;
	IOP[18] : TCO_REQUIREMENT = 999.9ns;
	IOP[19] : TCO_REQUIREMENT = 999.9ns;
	IOP[110] : TCO_REQUIREMENT = 999.9ns;
	IOP[111] : TCO_REQUIREMENT = 999.9ns;
	IOP[112] : TCO_REQUIREMENT = 999.9ns;
	IOP[113] : TCO_REQUIREMENT = 999.9ns;
	IOP[114] : TCO_REQUIREMENT = 999.9ns;
	IOP[115] : TCO_REQUIREMENT = 999.9ns;
	IOP[116] : TCO_REQUIREMENT = 999.9ns;
	IOP[117] : TCO_REQUIREMENT = 999.9ns;
	IOP[118] : TCO_REQUIREMENT = 999.9ns;
	IOP[119] : TCO_REQUIREMENT = 999.9ns;
	IOP[120] : TCO_REQUIREMENT = 999.9ns;
	IOP[121] : TCO_REQUIREMENT = 999.9ns;
	IOP[122] : TCO_REQUIREMENT = 999.9ns;
	IOP[123] : TCO_REQUIREMENT = 999.9ns;
	IOP[124] : TCO_REQUIREMENT = 999.9ns;
	IOP[125] : TCO_REQUIREMENT = 999.9ns;
	IOP[126] : TCO_REQUIREMENT = 999.9ns;
	IOP[127] : TCO_REQUIREMENT = 999.9ns;
	IOP[128] : TCO_REQUIREMENT = 999.9ns;
	IOP[129] : TCO_REQUIREMENT = 999.9ns;
	IOP[130] : TCO_REQUIREMENT = 999.9ns;
	IOP[131] : TCO_REQUIREMENT = 999.9ns;
	IOP[132] : TCO_REQUIREMENT = 999.9ns;
	IOP[133] : TCO_REQUIREMENT = 999.9ns;
	IOP[134] : TCO_REQUIREMENT = 999.9ns;
	IOP[135] : TCO_REQUIREMENT = 999.9ns;
	IOP[136] : TCO_REQUIREMENT = 999.9ns;
	IOP[20] : TCO_REQUIREMENT = 999.9ns;
	IOP[21] : TCO_REQUIREMENT = 999.9ns;
	IOP[22] : TCO_REQUIREMENT = 999.9ns;
	IOP[23] : TCO_REQUIREMENT = 999.9ns;
	IOP[24] : TCO_REQUIREMENT = 999.9ns;
	IOP[25] : TCO_REQUIREMENT = 999.9ns;
	IOP[26] : TCO_REQUIREMENT = 999.9ns;
	IOP[27] : TCO_REQUIREMENT = 999.9ns;
	IOP[28] : TCO_REQUIREMENT = 999.9ns;
	IOP[29] : TCO_REQUIREMENT = 999.9ns;
	IOP[210] : TCO_REQUIREMENT = 999.9ns;
	IOP[211] : TCO_REQUIREMENT = 999.9ns;
	IOP[212] : TCO_REQUIREMENT = 999.9ns;
	IOP[213] : TCO_REQUIREMENT = 999.9ns;
	IOP[214] : TCO_REQUIREMENT = 999.9ns;
	IOP[215] : TCO_REQUIREMENT = 999.9ns;
	IOP[216] : TCO_REQUIREMENT = 999.9ns;
	IOP[217] : TCO_REQUIREMENT = 999.9ns;
	IOP[218] : TCO_REQUIREMENT = 999.9ns;
	IOP[219] : TCO_REQUIREMENT = 999.9ns;
	IOP[220] : TCO_REQUIREMENT = 999.9ns;
	IOP[221] : TCO_REQUIREMENT = 999.9ns;
	IOP[222] : TCO_REQUIREMENT = 999.9ns;
	IOP[223] : TCO_REQUIREMENT = 999.9ns;
	IOP[224] : TCO_REQUIREMENT = 999.9ns;
	IOP[225] : TCO_REQUIREMENT = 999.9ns;
	IOP[226] : TCO_REQUIREMENT = 999.9ns;
	IOP[227] : TCO_REQUIREMENT = 999.9ns;
	IOP[228] : TCO_REQUIREMENT = 999.9ns;
	IOP[229] : TCO_REQUIREMENT = 999.9ns;
	IOP[230] : TCO_REQUIREMENT = 999.9ns;
	IOP[231] : TCO_REQUIREMENT = 999.9ns;
	IOP[232] : TCO_REQUIREMENT = 999.9ns;
	IOP[233] : TCO_REQUIREMENT = 999.9ns;
	IOP[234] : TCO_REQUIREMENT = 999.9ns;
	IOP[235] : TCO_REQUIREMENT = 999.9ns;
	IOP[236] : TCO_REQUIREMENT = 999.9ns;
	reset : TSU_REQUIREMENT = 999.9ns;
	mclk : TSU_REQUIREMENT = 999.9ns;
	wr : TSU_REQUIREMENT = 999.9ns;
	rd : TSU_REQUIREMENT = 999.9ns;
	cs : TSU_REQUIREMENT = 999.9ns;
	unused[0] : TSU_REQUIREMENT = 999.9ns;
	unused[1] : TSU_REQUIREMENT = 999.9ns;
	unused[2] : TSU_REQUIREMENT = 999.9ns;
	unused[3] : TSU_REQUIREMENT = 999.9ns;
	unused[4] : TSU_REQUIREMENT = 999.9ns;
	unused[5] : TSU_REQUIREMENT = 999.9ns;
	data[0] : TSU_REQUIREMENT = 999.9ns;
	data[1] : TSU_REQUIREMENT = 999.9ns;
	data[2] : TSU_REQUIREMENT = 999.9ns;
	data[3] : TSU_REQUIREMENT = 999.9ns;
	data[4] : TSU_REQUIREMENT = 999.9ns;
	data[5] : TSU_REQUIREMENT = 999.9ns;
	data[6] : TSU_REQUIREMENT = 999.9ns;
	data[7] : TSU_REQUIREMENT = 999.9ns;
	data[8] : TSU_REQUIREMENT = 999.9ns;
	data[9] : TSU_REQUIREMENT = 999.9ns;
	data[10] : TSU_REQUIREMENT = 999.9ns;
	data[11] : TSU_REQUIREMENT = 999.9ns;
	data[12] : TSU_REQUIREMENT = 999.9ns;
	data[13] : TSU_REQUIREMENT = 999.9ns;
	data[14] : TSU_REQUIREMENT = 999.9ns;
	data[15] : TSU_REQUIREMENT = 999.9ns;
	user_in[0] : TSU_REQUIREMENT = 999.9ns;
	user_in[1] : TSU_REQUIREMENT = 999.9ns;
	user_in[2] : TSU_REQUIREMENT = 999.9ns;
	user_in[3] : TSU_REQUIREMENT = 999.9ns;
	address[0] : TSU_REQUIREMENT = 999.9ns;
	address[1] : TSU_REQUIREMENT = 999.9ns;
	address[2] : TSU_REQUIREMENT = 999.9ns;
	address[3] : TSU_REQUIREMENT = 999.9ns;
	address[4] : TSU_REQUIREMENT = 999.9ns;
	address[5] : TSU_REQUIREMENT = 999.9ns;
	address[6] : TSU_REQUIREMENT = 999.9ns;
	address[7] : TSU_REQUIREMENT = 999.9ns;
	address[8] : TSU_REQUIREMENT = 999.9ns;
	address[9] : TSU_REQUIREMENT = 999.9ns;
	mclk : CLOCK_SETTINGS = mclk;
	switch[0] : TSU_REQUIREMENT = 999.9ns;
	switch[1] : TSU_REQUIREMENT = 999.9ns;
	switch[2] : TSU_REQUIREMENT = 999.9ns;
	switch[3] : TSU_REQUIREMENT = 999.9ns;
}