armexio.map.eqn

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· EQN 代码 · 共 2,809 行 · 第 1/5 页

--C07L1 is lpm_latch:iop2_29_|q[0]~1
--operation mode is normal

C07L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_13_ # !un1_wr_5_0_and2_0_and2 & C07L1);


--C17L1 is lpm_latch:iop2_30_|q[0]~1
--operation mode is normal

C17L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_14_ # !un1_wr_5_0_and2_0_and2 & C17L1);


--C27L1 is lpm_latch:iop2_31_|q[0]~1
--operation mode is normal

C27L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_15_ # !un1_wr_5_0_and2_0_and2 & C27L1);


--G_365 is G_365
--operation mode is normal

G_365 = G_355_lc & G_356_lc;


--C37L1 is lpm_latch:iop3_0_|q[0]~1
--operation mode is normal

C37L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_0_ # !A1L213 & C37L1);


--C47L1 is lpm_latch:iop3_1_|q[0]~1
--operation mode is normal

C47L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_1_ # !A1L213 & C47L1);


--C57L1 is lpm_latch:iop3_2_|q[0]~1
--operation mode is normal

C57L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_2_ # !A1L213 & C57L1);


--C67L1 is lpm_latch:iop3_3_|q[0]~1
--operation mode is normal

C67L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_3_ # !A1L213 & C67L1);


--C77L1 is lpm_latch:iop3_4_|q[0]~1
--operation mode is normal

C77L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_4_ # !A1L213 & C77L1);


--C87L1 is lpm_latch:iop3_5_|q[0]~1
--operation mode is normal

C87L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_5_ # !A1L213 & C87L1);


--C97L1 is lpm_latch:iop3_6_|q[0]~1
--operation mode is normal

C97L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_6_ # !A1L213 & C97L1);


--C08L1 is lpm_latch:iop3_7_|q[0]~1
--operation mode is normal

C08L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_7_ # !A1L213 & C08L1);


--C18L1 is lpm_latch:iop3_8_|q[0]~1
--operation mode is normal

C18L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_8_ # !A1L213 & C18L1);


--C28L1 is lpm_latch:iop3_9_|q[0]~1
--operation mode is normal

C28L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_9_ # !A1L213 & C28L1);


--C38L1 is lpm_latch:iop3_10_|q[0]~1
--operation mode is normal

C38L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_10_ # !A1L213 & C38L1);


--C48L1 is lpm_latch:iop3_11_|q[0]~1
--operation mode is normal

C48L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_11_ # !A1L213 & C48L1);


--C58L1 is lpm_latch:iop3_12_|q[0]~1
--operation mode is normal

C58L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_12_ # !A1L213 & C58L1);


--C68L1 is lpm_latch:iop3_13_|q[0]~1
--operation mode is normal

C68L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_13_ # !A1L213 & C68L1);


--C78L1 is lpm_latch:iop3_14_|q[0]~1
--operation mode is normal

C78L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_14_ # !A1L213 & C78L1);


--C88L1 is lpm_latch:iop3_15_|q[0]~1
--operation mode is normal

C88L1 = !un1_wr_6_0_and2_0_and2 & (A1L213 & data_15_ # !A1L213 & C88L1);


--C98L1 is lpm_latch:iop3_16_|q[0]~1
--operation mode is normal

C98L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_0_ # !A1L113 & C98L1);


--C09L1 is lpm_latch:iop3_17_|q[0]~1
--operation mode is normal

C09L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_1_ # !A1L113 & C09L1);


--C19L1 is lpm_latch:iop3_18_|q[0]~1
--operation mode is normal

C19L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_2_ # !A1L113 & C19L1);


--C29L1 is lpm_latch:iop3_19_|q[0]~1
--operation mode is normal

C29L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_3_ # !A1L113 & C29L1);


--C39L1 is lpm_latch:iop3_20_|q[0]~1
--operation mode is normal

C39L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_4_ # !A1L113 & C39L1);


--C49L1 is lpm_latch:iop3_21_|q[0]~1
--operation mode is normal

C49L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_5_ # !A1L113 & C49L1);


--C59L1 is lpm_latch:iop3_22_|q[0]~1
--operation mode is normal

C59L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_6_ # !A1L113 & C59L1);


--C69L1 is lpm_latch:iop3_23_|q[0]~1
--operation mode is normal

C69L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_7_ # !A1L113 & C69L1);


--C79L1 is lpm_latch:iop3_24_|q[0]~1
--operation mode is normal

C79L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_8_ # !A1L113 & C79L1);


--C89L1 is lpm_latch:iop3_25_|q[0]~1
--operation mode is normal

C89L1 = !un1_wr_6_0_and2_0_and2 & (A1L113 & data_9_ # !A1L113 & C89L1);


--led_cnt1_0_ is led_cnt1_0_
--operation mode is normal

led_cnt1_0__lut_out = !led_cnt1_1_ & !led_cnt1_0_;
led_cnt1_0_ = DFFEA(led_cnt1_0__lut_out, !mclk, , , un1_cnt3_2_0, , );


--led_cnt1_1_ is led_cnt1_1_
--operation mode is normal

led_cnt1_1__lut_out = !led_cnt1_1_ & led_cnt1_0_;
led_cnt1_1_ = DFFEA(led_cnt1_1__lut_out, !mclk, , , un1_cnt3_2_0, , );


--un1_iop1_6_0_i_0_0_540 is un1_iop1_6_0_i_0_0_540
--operation mode is normal

un1_iop1_6_0_i_0_0_540 = address[0] & C52L1 # !address[0] & C9L1 # !G_353;


--un1_iop1_6_0_i_0_and2_3_0_ is un1_iop1_6_0_i_0_and2_3_0_
--operation mode is normal

un1_iop1_6_0_i_0_and2_3_0_ = !C14L1 & !address[0] & !address[2] & address[1];


--un1_iop1_6_0_i_0_and2_2_0_ is un1_iop1_6_0_i_0_and2_2_0_
--operation mode is normal

un1_iop1_6_0_i_0_and2_2_0_ = !C75L1 & address[0] & !address[2] & address[1];


--un1_iop1_6_0_i_0_0_ is un1_iop1_6_0_i_0_0_
--operation mode is normal

un1_iop1_6_0_i_0_0_ = A1L542 & un1_iop1_6_0_i_0_0_540 & !un1_iop1_6_0_i_0_and2_3_0_ & !un1_iop1_6_0_i_0_and2_2_0_;


--un1_un30_rd_0_and2_0_1_512 is un1_un30_rd_0_and2_0_1_512
--operation mode is normal

un1_un30_rd_0_and2_0_1_512 = G_352 & (!address[1] # !address[2]);


--un1_un30_rd_0_and2_0_15_ is un1_un30_rd_0_and2_0_15_
--operation mode is normal

un1_un30_rd_0_and2_0_15_ = !rd & !cs & (un1_un30_rd_0_and2_0_1_512 # G_356_lc);


--un1_iop1_6_0_0_0_8_573 is un1_iop1_6_0_0_0_8_573
--operation mode is normal

un1_iop1_6_0_0_0_8_573 = address[0] & !C33L1 # !address[0] & !C71L1 # !G_353;


--un1_iop1_6_0_0_0_8_572 is un1_iop1_6_0_0_0_8_572
--operation mode is normal

un1_iop1_6_0_0_0_8_572 = address[0] & !C79L1 # !address[0] & !C18L1 # !G_355_lc;


--un1_iop1_6_0_0_0_8_ is un1_iop1_6_0_0_0_8_
--operation mode is normal

un1_iop1_6_0_0_0_8_ = !un1_iop1_6_0_0_0_8_572 # !un1_iop1_6_0_0_0_8_573 # !A1L432;


--un1_iop1_6_0_0_0_and2_2_9_ is un1_iop1_6_0_0_0_and2_2_9_
--operation mode is normal

un1_iop1_6_0_0_0_and2_2_9_ = C05L1 & !address[0] & !address[2] & address[1];


--un1_iop1_6_0_0_0_and2_1_9_ is un1_iop1_6_0_0_0_and2_1_9_
--operation mode is normal

un1_iop1_6_0_0_0_and2_1_9_ = C66L1 & address[0] & !address[2] & address[1];


--un1_iop1_6_0_0_0_9_569 is un1_iop1_6_0_0_0_9_569
--operation mode is normal

un1_iop1_6_0_0_0_9_569 = address[0] & !C43L1 # !address[0] & !C81L1 # !G_353;


--un1_iop1_6_0_0_0_9_568 is un1_iop1_6_0_0_0_9_568
--operation mode is normal

un1_iop1_6_0_0_0_9_568 = address[0] & !C89L1 # !address[0] & !C28L1 # !G_355_lc;


--un1_iop1_6_0_0_0_9_ is un1_iop1_6_0_0_0_9_
--operation mode is normal

un1_iop1_6_0_0_0_9_ = un1_iop1_6_0_0_0_and2_2_9_ # un1_iop1_6_0_0_0_and2_1_9_ # !un1_iop1_6_0_0_0_9_568 # !un1_iop1_6_0_0_0_9_569;


--un1_iop1_iv_0_0_10_578 is un1_iop1_iv_0_0_10_578
--operation mode is normal

un1_iop1_iv_0_0_10_578 = C76L1 & !G_369 & (!G_366 # !C15L1) # !C76L1 & (!G_366 # !C15L1);


--un1_iop1_iv_0_0_10_579 is un1_iop1_iv_0_0_10_579
--operation mode is normal

un1_iop1_iv_0_0_10_579 = C38L1 & !G_365 & (!A1L56 # !C53L1) # !C38L1 & (!A1L56 # !C53L1);


--un1_iop1_iv_0_0_10_ is un1_iop1_iv_0_0_10_
--operation mode is normal

un1_iop1_iv_0_0_10_ = C91L1 & A1L46 # !un1_iop1_iv_0_0_10_579 # !un1_iop1_iv_0_0_10_578;


--un1_iop1_iv_0_0_11_575 is un1_iop1_iv_0_0_11_575
--operation mode is normal

un1_iop1_iv_0_0_11_575 = C86L1 & !G_369 & (!G_366 # !C25L1) # !C86L1 & (!G_366 # !C25L1);


--un1_iop1_iv_0_0_11_576 is un1_iop1_iv_0_0_11_576
--operation mode is normal

un1_iop1_iv_0_0_11_576 = C48L1 & !G_365 & (!A1L56 # !C63L1) # !C48L1 & (!A1L56 # !C63L1);


--un1_iop1_iv_0_0_11_ is un1_iop1_iv_0_0_11_
--operation mode is normal

un1_iop1_iv_0_0_11_ = C02L1 & A1L46 # !un1_iop1_iv_0_0_11_576 # !un1_iop1_iv_0_0_11_575;


--un1_iop1_iv_0_0_12_558 is un1_iop1_iv_0_0_12_558
--operation mode is normal

un1_iop1_iv_0_0_12_558 = C96L1 & !G_369 & (!G_366 # !C35L1) # !C96L1 & (!G_366 # !C35L1);


--un1_iop1_iv_0_0_12_559 is un1_iop1_iv_0_0_12_559
--operation mode is normal

un1_iop1_iv_0_0_12_559 = C58L1 & !G_365 & (!A1L56 # !C73L1) # !C58L1 & (!A1L56 # !C73L1);


--un1_iop1_iv_0_0_12_ is un1_iop1_iv_0_0_12_
--operation mode is normal

un1_iop1_iv_0_0_12_ = C12L1 & A1L46 # !un1_iop1_iv_0_0_12_559 # !un1_iop1_iv_0_0_12_558;


--un1_iop1_iv_0_0_13_555 is un1_iop1_iv_0_0_13_555
--operation mode is normal

un1_iop1_iv_0_0_13_555 = C07L1 & !G_369 & (!G_366 # !C45L1) # !C07L1 & (!G_366 # !C45L1);


--un1_iop1_iv_0_0_13_556 is un1_iop1_iv_0_0_13_556
--operation mode is normal

un1_iop1_iv_0_0_13_556 = C68L1 & !G_365 & (!A1L56 # !C83L1) # !C68L1 & (!A1L56 # !C83L1);


--un1_iop1_iv_0_0_13_ is un1_iop1_iv_0_0_13_
--operation mode is normal

un1_iop1_iv_0_0_13_ = C22L1 & A1L46 # !un1_iop1_iv_0_0_13_556 # !un1_iop1_iv_0_0_13_555;


--un1_iop1_iv_0_0_14_564 is un1_iop1_iv_0_0_14_564
--operation mode is normal

un1_iop1_iv_0_0_14_564 = C17L1 & !G_369 & (!G_366 # !C55L1) # !C17L1 & (!G_366 # !C55L1);


--un1_iop1_iv_0_0_14_565 is un1_iop1_iv_0_0_14_565
--operation mode is normal

un1_iop1_iv_0_0_14_565 = C78L1 & !G_365 & (!A1L56 # !C93L1) # !C78L1 & (!A1L56 # !C93L1);


--un1_iop1_iv_0_0_14_ is un1_iop1_iv_0_0_14_
--operation mode is normal

un1_iop1_iv_0_0_14_ = C32L1 & A1L46 # !un1_iop1_iv_0_0_14_565 # !un1_iop1_iv_0_0_14_564;


--un1_iop1_iv_0_0_15_561 is un1_iop1_iv_0_0_15_561
--operation mode is normal

un1_iop1_iv_0_0_15_561 = C27L1 & !G_369 & (!G_366 # !C65L1) # !C27L1 & (!G_366 # !C65L1);


--un1_iop1_iv_0_0_15_562 is un1_iop1_iv_0_0_15_562
--operation mode is normal

un1_iop1_iv_0_0_15_562 = C88L1 & !G_365 & (!A1L56 # !C04L1) # !C88L1 & (!A1L56 # !C04L1);


--un1_iop1_iv_0_0_15_ is un1_iop1_iv_0_0_15_
--operation mode is normal

un1_iop1_iv_0_0_15_ = C42L1 & A1L46 # !un1_iop1_iv_0_0_15_562 # !un1_iop1_iv_0_0_15_561;


--G_350_504 is G_350_504
--operation mode is normal

G_350_504 = !address[5] & !address[9] & !address[8] & !address[7];


--G_350_lc is G_350_lc
--operation mode is normal

G_350_lc = G_350_504 & !address[6];

--A1L35 is G_350_lc~0
--operation mode is normal

A1L35 = G_350_504 & !address[6];


--G_355_lc is G_355_lc
--operation mode is normal

G_355_lc = address[2] & !address[1];

--A1L85 is G_355_lc~0
--operation mode is normal

A1L85 = address[2] & !address[1];


--led_un1_cnt2_lt7_cry is led_un1_cnt2_lt7_cry
--operation mode is arithmetic

led_un1_cnt2_lt7_cry = un2_cnt2_cry_1_ & C8L1 & led_un1_cnt2_lt6_cry # !un2_cnt2_cry_1_ & (C8L1 # led_un1_cnt2_lt6_cry);

--A1L222 is led_un1_cnt2_lt7_cry~COUT
--operation mode is arithmetic

A1L222 = CARRY(un2_cnt2_cry_1_ & C8L1 & led_un1_cnt2_lt6_cry # !un2_cnt2_cry_1_ & (C8L1 # led_un1_cnt2_lt6_cry));


--un1_cnt3_2_0 is un1_cnt3_2_0
--operation mode is normal

un1_cnt3_2_0 = A1L94 & !A1L222;


--A1L713 is un1_wr_6_0_and2_0_and2_508~0
--operation mode is normal

A1L713 = (address[2] & address[1] & address[4] & address[3]) & CASCADE(A1L35);


--A1L113 is un1_wr_1_0_and2_0_and2~60
--operation mode is normal

A1L113 = (!wr & !cs & G_352 & address[0]) & CASCADE(A1L85);


--un1_iop1_6_0_i_0_and2_i_0_ is un1_iop1_6_0_i_0_and2_i_0_
--operation mode is normal

un1_iop1_6_0_i_0_and2_i_0_ = C1L1 # !address[1] # !address[2];


--A1L542 is un1_iop1_6_0_i_0_0_543~0
--operation mode is normal

A1L542 = (address[0] & C98L1 # !address[0] & C37L1 # !G_355_lc) & CASCADE(un1_iop1_6_0_i_0_and2_i_0_);


--un1_iop1_6_0_i_0_and2_1_1_ is un1_iop1_6_0_i_0_and2_1_1_
--operation mode is normal

un1_iop1_6_0_i_0_and2_1_1_ = !C47L1 & !address[0] & G_355_lc;


--un1_iop1_6_0_i_0_1_537 is un1_iop1_6_0_i_0_1_537
--operation mode is normal

un1_iop1_6_0_i_0_1_537 = !un1_iop1_6_0_i_0_and2_1_1_ & (C2L1 # !address[1] # !address[2]);


--A1L942 is un1_iop1_6_0_i_0_1_~0
--operation mode is normal

A1L942 = (un1_iop1_6_0_i_0_1_537 & (C09L1 # !G_355_lc # !address[0])) & CASCADE(A1L842);


--un1_iop1_6_0_i_0_and2_1_2_ is un1_iop1_6_0_i_0_and2_1_2_
--operation mode is normal

un1_iop1_6_0_i_0_and2_1_2_ = !C57L1 & !address[0] & G_355_lc;


--un1_iop1_6_0_i_0_2_552 is un1_iop1_6_0_i_0_2_552
--operation mode is normal

un1_iop1_6_0_i_0_2_552 = !un1_iop1_6_0_i_0_and2_1_2_ & (C3L1 # !address[1] # !address[2]);


--A1L352 is un1_iop1_6_0_i_0_2_~0
--operation mode is normal

A1L352 = (un1_iop1_6_0_i_0_2_552 & (C19L1 # !G_355_lc # !address[0])) & CASCADE(A1L252);


--un1_iop1_6_0_i_0_and2_1_3_ is un1_iop1_6_0_i_0_and2_1_3_
--operation mode is normal

un1_iop1_6_0_i_0_and2_1_3_ = !C67L1 & !address[0] & G_355_lc;


--un1_iop1_6_0_i_0_3_547 is un1_iop1_6_0_i_0_3_547
--operation mode is normal

un1_iop1_6_0_i_0_3_547 = !un1_iop1_6_0_i_0_and2_1_3_ & (C4L1 # !address[1] # !address[2]);


--A1L752 is un1_iop1_6_0_i_0_3_~0
--operation mode is normal

A1L752 = (un1_iop1_6_0_i_0_3_547 & (C29L1 # !G_355_lc # !address[0])) & CASCADE(A1L652);


--un1_iop1_6_0_i_0_and2_1_4_ is un1_iop1_6_0_i_0_and2_1_4_
--operation mode is normal

un1_iop1_6_0_i_0_and2_1_4_ = !C77L1 & !address[0] & G_355_lc;


--un1_iop1_6_0_i_0_4_522 is un1_iop1_6_0_i_0_4_522
--operation mode is normal

un1_iop1_6_0_i_0_4_522 = !un1_iop1_6_0_i_0_and2_1_4_ & (C5L1 # !address[1] # !address[2]);


--A1L162 is un1_iop1_6_0_i_0_4_~0
--operation mode is normal

A1L162 = (un1_iop1_6_0_i_0_4_522 & (C39L1 # !G_355_lc # !address[0])) & CASCADE(A1L062);


--un1_iop1_6_0_i_0_and2_1_5_ is un1_iop1_6_0_i_0_and2_1_5_
--operation mode is normal

un1_iop1_6_0_i_0_and2_1_5_ = !C87L1 & !address[0] & G_355_lc;


--un1_iop1_6_0_i_0_5_517 is un1_iop1_6_0_i_0_5_517
--operation mode is normal

un1_iop1_6_0_i_0_5_517 = !un1_iop1_6_0_i_0_and2_1_5_ & (C6L1 # !address[1] # !address[2]);


--A1L562 is un1_iop1_6_0_i_0_5_~0
--operation mode is normal

A1L562 = (un1_iop1_6_0_i_0_5_517 & (C49L1 # !G_355_lc # !address[0])) & CASCADE(A1L462);


--un1_iop1_6_0_i_0_and2_1_6_ is un1_iop1_6_0_i_0_and2_1_6_
--operation mode is normal

un1_iop1_6_0_i_0_and2_1_6_ = !C97L1 & !address[0] & G_355_lc;


--un1_iop1_6_0_i_0_6_532 is un1_iop1_6_0_i_0_6_532
--operation mode is normal

un1_iop1_6_0_i_0_6_532 = !un1_iop1_6_0_i_0_and2_1_6_ & (C7L1 # !address[1] # !address[2]);


--A1L962 is un1_iop1_6_0_i_0_6_~0
--operation mode is normal

A1L962 = (un1_iop1_6_0_i_0_6_532 & (C59L1 # !G_355_lc # !address[0])) & CASCADE(A1L862);