armexio.map.eqn

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· EQN 代码 · 共 2,809 行 · 第 1/5 页

--A1L022 is led_un1_cnt2_lt6_cry~4
--operation mode is arithmetic

A1L022 = un2_cnt2_cry_2_ & C7L1 & led_un1_cnt2_lt5_cry # !un2_cnt2_cry_2_ & (C7L1 # led_un1_cnt2_lt5_cry);

--led_un1_cnt2_lt6_cry is led_un1_cnt2_lt6_cry
--operation mode is arithmetic

led_un1_cnt2_lt6_cry = CARRY(un2_cnt2_cry_2_ & C7L1 & led_un1_cnt2_lt5_cry # !un2_cnt2_cry_2_ & (C7L1 # led_un1_cnt2_lt5_cry));


--A1L812 is led_un1_cnt2_lt5_cry~1
--operation mode is arithmetic

A1L812 = un2_cnt2_cry_3_ & C6L1 & led_un1_cnt2_lt4_cry # !un2_cnt2_cry_3_ & (C6L1 # led_un1_cnt2_lt4_cry);

--led_un1_cnt2_lt5_cry is led_un1_cnt2_lt5_cry
--operation mode is arithmetic

led_un1_cnt2_lt5_cry = CARRY(un2_cnt2_cry_3_ & C6L1 & led_un1_cnt2_lt4_cry # !un2_cnt2_cry_3_ & (C6L1 # led_un1_cnt2_lt4_cry));


--A1L612 is led_un1_cnt2_lt4_cry~1
--operation mode is arithmetic

A1L612 = un2_cnt2_cry_4_ & C5L1 & led_un1_cnt2_lt3_cry # !un2_cnt2_cry_4_ & (C5L1 # led_un1_cnt2_lt3_cry);

--led_un1_cnt2_lt4_cry is led_un1_cnt2_lt4_cry
--operation mode is arithmetic

led_un1_cnt2_lt4_cry = CARRY(un2_cnt2_cry_4_ & C5L1 & led_un1_cnt2_lt3_cry # !un2_cnt2_cry_4_ & (C5L1 # led_un1_cnt2_lt3_cry));


--A1L412 is led_un1_cnt2_lt3_cry~1
--operation mode is arithmetic

A1L412 = un2_cnt2_cry_5_ & C4L1 & led_un1_cnt2_lt2_cry # !un2_cnt2_cry_5_ & (C4L1 # led_un1_cnt2_lt2_cry);

--led_un1_cnt2_lt3_cry is led_un1_cnt2_lt3_cry
--operation mode is arithmetic

led_un1_cnt2_lt3_cry = CARRY(un2_cnt2_cry_5_ & C4L1 & led_un1_cnt2_lt2_cry # !un2_cnt2_cry_5_ & (C4L1 # led_un1_cnt2_lt2_cry));


--A1L212 is led_un1_cnt2_lt2_cry~1
--operation mode is arithmetic

A1L212 = un2_cnt2_cry_6_ & C3L1 & led_un1_cnt2_lt1_cry # !un2_cnt2_cry_6_ & (C3L1 # led_un1_cnt2_lt1_cry);

--led_un1_cnt2_lt2_cry is led_un1_cnt2_lt2_cry
--operation mode is arithmetic

led_un1_cnt2_lt2_cry = CARRY(un2_cnt2_cry_6_ & C3L1 & led_un1_cnt2_lt1_cry # !un2_cnt2_cry_6_ & (C3L1 # led_un1_cnt2_lt1_cry));


--A1L012 is led_un1_cnt2_lt1_cry~1
--operation mode is arithmetic

A1L012 = un2_cnt2_cry_7_ & C2L1 & led_un1_cnt2_lt0_cry # !un2_cnt2_cry_7_ & (C2L1 # led_un1_cnt2_lt0_cry);

--led_un1_cnt2_lt1_cry is led_un1_cnt2_lt1_cry
--operation mode is arithmetic

led_un1_cnt2_lt1_cry = CARRY(un2_cnt2_cry_7_ & C2L1 & led_un1_cnt2_lt0_cry # !un2_cnt2_cry_7_ & (C2L1 # led_un1_cnt2_lt0_cry));


--A1L933 is un6_cnt3_cry_14_~2
--operation mode is arithmetic

A1L933 = led_cnt3_18_ $ A1L343;

--un6_cnt3_cry_14_ is un6_cnt3_cry_14_
--operation mode is arithmetic

un6_cnt3_cry_14_ = CARRY(led_cnt3_18_ $ A1L343);


--A1L733 is un6_cnt3_cry_13_~2
--operation mode is arithmetic

A1L733 = led_cnt3_19_ $ (led_cnt3_18_ & A1L143);

--un6_cnt3_cry_13_ is un6_cnt3_cry_13_
--operation mode is arithmetic

un6_cnt3_cry_13_ = CARRY(led_cnt3_19_ $ (led_cnt3_18_ & A1L143));


--A1L533 is un2_cnt2_cry_8_~4
--operation mode is arithmetic

A1L533 = led_cnt2_0_ & led_cnt2_1_;

--un2_cnt2_cry_8_ is un2_cnt2_cry_8_
--operation mode is arithmetic

un2_cnt2_cry_8_ = CARRY(led_cnt2_0_ & led_cnt2_1_);


--A1L573 is un6_cnt3_cry_32_~4
--operation mode is arithmetic

A1L573 = led_cnt3_0_ & led_cnt3_1_;

--un6_cnt3_cry_32_ is un6_cnt3_cry_32_
--operation mode is arithmetic

un6_cnt3_cry_32_ = CARRY(led_cnt3_0_ & led_cnt3_1_);


--A1L802 is led_un1_cnt2_lt0_cry~1
--operation mode is arithmetic

A1L802 = C1L1 & led_cnt2_0_;

--led_un1_cnt2_lt0_cry is led_un1_cnt2_lt0_cry
--operation mode is arithmetic

led_un1_cnt2_lt0_cry = CARRY(C1L1 & led_cnt2_0_);


--led_aaaa_0_ is led_aaaa_0_
--operation mode is normal

led_aaaa_0__lut_out = led_cnt1_1_ & (led_aaaa_0_ # !led_cnt1_0_) # !led_cnt1_1_ & led_cnt1_0_;
led_aaaa_0_ = DFFEA(led_aaaa_0__lut_out, !mclk, , , un1_cnt3_2_0, , );


--led_aaaa_1_ is led_aaaa_1_
--operation mode is normal

led_aaaa_1__lut_out = led_aaaa_1_ & led_cnt1_1_ # !led_cnt1_0_;
led_aaaa_1_ = DFFEA(led_aaaa_1__lut_out, !mclk, , , un1_cnt3_2_0, , );


--led_aaaa_2_ is led_aaaa_2_
--operation mode is normal

led_aaaa_2__lut_out = led_aaaa_2_ & led_cnt1_0_ # !led_cnt1_1_;
led_aaaa_2_ = DFFEA(led_aaaa_2__lut_out, !mclk, , , un1_cnt3_2_0, , );


--G_353 is G_353
--operation mode is normal

G_353 = !address[1] & !address[2];


--un1_wr_3_0_and2_0_and2 is un1_wr_3_0_and2_0_and2
--operation mode is normal

un1_wr_3_0_and2_0_and2 = A1L46 & !wr & !cs;


--un1_wr_6_0_and2_0_and2 is un1_wr_6_0_and2_0_and2
--operation mode is normal

un1_wr_6_0_and2_0_and2 = address[0] & A1L713 & !wr & !cs;


--C9L1 is lpm_latch:iop1_0_|q[0]~1
--operation mode is normal

C9L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_0_ # !un1_wr_3_0_and2_0_and2 & C9L1);


--C01L1 is lpm_latch:iop1_1_|q[0]~1
--operation mode is normal

C01L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_1_ # !un1_wr_3_0_and2_0_and2 & C01L1);


--C11L1 is lpm_latch:iop1_2_|q[0]~1
--operation mode is normal

C11L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_2_ # !un1_wr_3_0_and2_0_and2 & C11L1);


--C21L1 is lpm_latch:iop1_3_|q[0]~1
--operation mode is normal

C21L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_3_ # !un1_wr_3_0_and2_0_and2 & C21L1);


--C31L1 is lpm_latch:iop1_4_|q[0]~1
--operation mode is normal

C31L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_4_ # !un1_wr_3_0_and2_0_and2 & C31L1);


--C41L1 is lpm_latch:iop1_5_|q[0]~1
--operation mode is normal

C41L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_5_ # !un1_wr_3_0_and2_0_and2 & C41L1);


--C51L1 is lpm_latch:iop1_6_|q[0]~1
--operation mode is normal

C51L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_6_ # !un1_wr_3_0_and2_0_and2 & C51L1);


--C61L1 is lpm_latch:iop1_7_|q[0]~1
--operation mode is normal

C61L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_7_ # !un1_wr_3_0_and2_0_and2 & C61L1);


--C71L1 is lpm_latch:iop1_8_|q[0]~1
--operation mode is normal

C71L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_8_ # !un1_wr_3_0_and2_0_and2 & C71L1);


--C81L1 is lpm_latch:iop1_9_|q[0]~1
--operation mode is normal

C81L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_9_ # !un1_wr_3_0_and2_0_and2 & C81L1);


--C91L1 is lpm_latch:iop1_10_|q[0]~1
--operation mode is normal

C91L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_10_ # !un1_wr_3_0_and2_0_and2 & C91L1);


--C02L1 is lpm_latch:iop1_11_|q[0]~1
--operation mode is normal

C02L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_11_ # !un1_wr_3_0_and2_0_and2 & C02L1);


--C12L1 is lpm_latch:iop1_12_|q[0]~1
--operation mode is normal

C12L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_12_ # !un1_wr_3_0_and2_0_and2 & C12L1);


--C22L1 is lpm_latch:iop1_13_|q[0]~1
--operation mode is normal

C22L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_13_ # !un1_wr_3_0_and2_0_and2 & C22L1);


--C32L1 is lpm_latch:iop1_14_|q[0]~1
--operation mode is normal

C32L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_14_ # !un1_wr_3_0_and2_0_and2 & C32L1);


--C42L1 is lpm_latch:iop1_15_|q[0]~1
--operation mode is normal

C42L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_15_ # !un1_wr_3_0_and2_0_and2 & C42L1);


--G_352 is G_352
--operation mode is normal

G_352 = G_350_lc & !address[4] & !address[3];


--un1_wr_4_0_and2_0_and2 is un1_wr_4_0_and2_0_and2
--operation mode is normal

un1_wr_4_0_and2_0_and2 = A1L56 & !wr & !cs;


--C52L1 is lpm_latch:iop1_16_|q[0]~1
--operation mode is normal

C52L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_0_ # !un1_wr_4_0_and2_0_and2 & C52L1);


--C62L1 is lpm_latch:iop1_17_|q[0]~1
--operation mode is normal

C62L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_1_ # !un1_wr_4_0_and2_0_and2 & C62L1);


--C72L1 is lpm_latch:iop1_18_|q[0]~1
--operation mode is normal

C72L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_2_ # !un1_wr_4_0_and2_0_and2 & C72L1);


--C82L1 is lpm_latch:iop1_19_|q[0]~1
--operation mode is normal

C82L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_3_ # !un1_wr_4_0_and2_0_and2 & C82L1);


--C92L1 is lpm_latch:iop1_20_|q[0]~1
--operation mode is normal

C92L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_4_ # !un1_wr_4_0_and2_0_and2 & C92L1);


--C03L1 is lpm_latch:iop1_21_|q[0]~1
--operation mode is normal

C03L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_5_ # !un1_wr_4_0_and2_0_and2 & C03L1);


--C13L1 is lpm_latch:iop1_22_|q[0]~1
--operation mode is normal

C13L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_6_ # !un1_wr_4_0_and2_0_and2 & C13L1);


--C23L1 is lpm_latch:iop1_23_|q[0]~1
--operation mode is normal

C23L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_7_ # !un1_wr_4_0_and2_0_and2 & C23L1);


--C33L1 is lpm_latch:iop1_24_|q[0]~1
--operation mode is normal

C33L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_8_ # !un1_wr_4_0_and2_0_and2 & C33L1);


--C43L1 is lpm_latch:iop1_25_|q[0]~1
--operation mode is normal

C43L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_9_ # !un1_wr_4_0_and2_0_and2 & C43L1);


--C53L1 is lpm_latch:iop1_26_|q[0]~1
--operation mode is normal

C53L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_10_ # !un1_wr_4_0_and2_0_and2 & C53L1);


--C63L1 is lpm_latch:iop1_27_|q[0]~1
--operation mode is normal

C63L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_11_ # !un1_wr_4_0_and2_0_and2 & C63L1);


--C73L1 is lpm_latch:iop1_28_|q[0]~1
--operation mode is normal

C73L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_12_ # !un1_wr_4_0_and2_0_and2 & C73L1);


--C83L1 is lpm_latch:iop1_29_|q[0]~1
--operation mode is normal

C83L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_13_ # !un1_wr_4_0_and2_0_and2 & C83L1);


--C93L1 is lpm_latch:iop1_30_|q[0]~1
--operation mode is normal

C93L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_14_ # !un1_wr_4_0_and2_0_and2 & C93L1);


--C04L1 is lpm_latch:iop1_31_|q[0]~1
--operation mode is normal

C04L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_15_ # !un1_wr_4_0_and2_0_and2 & C04L1);


--G_366 is G_366
--operation mode is normal

G_366 = G_356_lc & !address[2] & address[1];


--un1_wr_7_0_and2_0_and2 is un1_wr_7_0_and2_0_and2
--operation mode is normal

un1_wr_7_0_and2_0_and2 = G_366 & !wr & !cs;


--C14L1 is lpm_latch:iop2_0_|q[0]~1
--operation mode is normal

C14L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_0_ # !un1_wr_7_0_and2_0_and2 & C14L1);


--C24L1 is lpm_latch:iop2_1_|q[0]~1
--operation mode is normal

C24L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_1_ # !un1_wr_7_0_and2_0_and2 & C24L1);


--C34L1 is lpm_latch:iop2_2_|q[0]~1
--operation mode is normal

C34L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_2_ # !un1_wr_7_0_and2_0_and2 & C34L1);


--C44L1 is lpm_latch:iop2_3_|q[0]~1
--operation mode is normal

C44L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_3_ # !un1_wr_7_0_and2_0_and2 & C44L1);


--C54L1 is lpm_latch:iop2_4_|q[0]~1
--operation mode is normal

C54L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_4_ # !un1_wr_7_0_and2_0_and2 & C54L1);


--C64L1 is lpm_latch:iop2_5_|q[0]~1
--operation mode is normal

C64L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_5_ # !un1_wr_7_0_and2_0_and2 & C64L1);


--C74L1 is lpm_latch:iop2_6_|q[0]~1
--operation mode is normal

C74L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_6_ # !un1_wr_7_0_and2_0_and2 & C74L1);


--C84L1 is lpm_latch:iop2_7_|q[0]~1
--operation mode is normal

C84L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_7_ # !un1_wr_7_0_and2_0_and2 & C84L1);


--C94L1 is lpm_latch:iop2_8_|q[0]~1
--operation mode is normal

C94L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_8_ # !un1_wr_7_0_and2_0_and2 & C94L1);


--C05L1 is lpm_latch:iop2_9_|q[0]~1
--operation mode is normal

C05L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_9_ # !un1_wr_7_0_and2_0_and2 & C05L1);


--C15L1 is lpm_latch:iop2_10_|q[0]~1
--operation mode is normal

C15L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_10_ # !un1_wr_7_0_and2_0_and2 & C15L1);


--C25L1 is lpm_latch:iop2_11_|q[0]~1
--operation mode is normal

C25L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_11_ # !un1_wr_7_0_and2_0_and2 & C25L1);


--C35L1 is lpm_latch:iop2_12_|q[0]~1
--operation mode is normal

C35L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_12_ # !un1_wr_7_0_and2_0_and2 & C35L1);


--C45L1 is lpm_latch:iop2_13_|q[0]~1
--operation mode is normal

C45L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_13_ # !un1_wr_7_0_and2_0_and2 & C45L1);


--C55L1 is lpm_latch:iop2_14_|q[0]~1
--operation mode is normal

C55L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_14_ # !un1_wr_7_0_and2_0_and2 & C55L1);


--C65L1 is lpm_latch:iop2_15_|q[0]~1
--operation mode is normal

C65L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_15_ # !un1_wr_7_0_and2_0_and2 & C65L1);


--G_369 is G_369
--operation mode is normal

G_369 = G_352 & address[0] & !address[2] & address[1];


--un1_wr_5_0_and2_0_and2 is un1_wr_5_0_and2_0_and2
--operation mode is normal

un1_wr_5_0_and2_0_and2 = G_369 & !wr & !cs;


--C75L1 is lpm_latch:iop2_16_|q[0]~1
--operation mode is normal

C75L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_0_ # !un1_wr_5_0_and2_0_and2 & C75L1);


--C85L1 is lpm_latch:iop2_17_|q[0]~1
--operation mode is normal

C85L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_1_ # !un1_wr_5_0_and2_0_and2 & C85L1);


--C95L1 is lpm_latch:iop2_18_|q[0]~1
--operation mode is normal

C95L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_2_ # !un1_wr_5_0_and2_0_and2 & C95L1);


--C06L1 is lpm_latch:iop2_19_|q[0]~1
--operation mode is normal

C06L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_3_ # !un1_wr_5_0_and2_0_and2 & C06L1);


--C16L1 is lpm_latch:iop2_20_|q[0]~1
--operation mode is normal

C16L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_4_ # !un1_wr_5_0_and2_0_and2 & C16L1);


--C26L1 is lpm_latch:iop2_21_|q[0]~1
--operation mode is normal

C26L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_5_ # !un1_wr_5_0_and2_0_and2 & C26L1);


--C36L1 is lpm_latch:iop2_22_|q[0]~1
--operation mode is normal

C36L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_6_ # !un1_wr_5_0_and2_0_and2 & C36L1);


--C46L1 is lpm_latch:iop2_23_|q[0]~1
--operation mode is normal

C46L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_7_ # !un1_wr_5_0_and2_0_and2 & C46L1);


--C56L1 is lpm_latch:iop2_24_|q[0]~1
--operation mode is normal

C56L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_8_ # !un1_wr_5_0_and2_0_and2 & C56L1);


--C66L1 is lpm_latch:iop2_25_|q[0]~1
--operation mode is normal

C66L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_9_ # !un1_wr_5_0_and2_0_and2 & C66L1);


--C76L1 is lpm_latch:iop2_26_|q[0]~1
--operation mode is normal

C76L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_10_ # !un1_wr_5_0_and2_0_and2 & C76L1);


--C86L1 is lpm_latch:iop2_27_|q[0]~1
--operation mode is normal

C86L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_11_ # !un1_wr_5_0_and2_0_and2 & C86L1);


--C96L1 is lpm_latch:iop2_28_|q[0]~1
--operation mode is normal

C96L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_12_ # !un1_wr_5_0_and2_0_and2 & C96L1);