armexio.fit.eqn

来自「usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全」· EQN 代码 · 共 2,642 行 · 第 1/5 页

--A1L522 is led_un1_cnt2_lt6_cry~4 at LC3_F7
--operation mode is arithmetic

A1L522 = C7L1 & (led_un1_cnt2_lt5_cry # !un2_cnt2_cry_2_) # !C7L1 & !un2_cnt2_cry_2_ & led_un1_cnt2_lt5_cry;

--led_un1_cnt2_lt6_cry is led_un1_cnt2_lt6_cry at LC3_F7
--operation mode is arithmetic

led_un1_cnt2_lt6_cry = CARRY(C7L1 & (led_un1_cnt2_lt5_cry # !un2_cnt2_cry_2_) # !C7L1 & !un2_cnt2_cry_2_ & led_un1_cnt2_lt5_cry);


--A1L322 is led_un1_cnt2_lt5_cry~1 at LC2_F7
--operation mode is arithmetic

A1L322 = C6L1 & (led_un1_cnt2_lt4_cry # !un2_cnt2_cry_3_) # !C6L1 & !un2_cnt2_cry_3_ & led_un1_cnt2_lt4_cry;

--led_un1_cnt2_lt5_cry is led_un1_cnt2_lt5_cry at LC2_F7
--operation mode is arithmetic

led_un1_cnt2_lt5_cry = CARRY(C6L1 & (led_un1_cnt2_lt4_cry # !un2_cnt2_cry_3_) # !C6L1 & !un2_cnt2_cry_3_ & led_un1_cnt2_lt4_cry);


--A1L122 is led_un1_cnt2_lt4_cry~1 at LC1_F7
--operation mode is arithmetic

A1L122 = C5L1 & (led_un1_cnt2_lt3_cry # !un2_cnt2_cry_4_) # !C5L1 & !un2_cnt2_cry_4_ & led_un1_cnt2_lt3_cry;

--led_un1_cnt2_lt4_cry is led_un1_cnt2_lt4_cry at LC1_F7
--operation mode is arithmetic

led_un1_cnt2_lt4_cry = CARRY(C5L1 & (led_un1_cnt2_lt3_cry # !un2_cnt2_cry_4_) # !C5L1 & !un2_cnt2_cry_4_ & led_un1_cnt2_lt3_cry);


--A1L912 is led_un1_cnt2_lt3_cry~1 at LC8_F5
--operation mode is arithmetic

A1L912 = C4L1 & (led_un1_cnt2_lt2_cry # !un2_cnt2_cry_5_) # !C4L1 & !un2_cnt2_cry_5_ & led_un1_cnt2_lt2_cry;

--led_un1_cnt2_lt3_cry is led_un1_cnt2_lt3_cry at LC8_F5
--operation mode is arithmetic

led_un1_cnt2_lt3_cry = CARRY(C4L1 & (led_un1_cnt2_lt2_cry # !un2_cnt2_cry_5_) # !C4L1 & !un2_cnt2_cry_5_ & led_un1_cnt2_lt2_cry);


--A1L712 is led_un1_cnt2_lt2_cry~1 at LC7_F5
--operation mode is arithmetic

A1L712 = C3L1 & (led_un1_cnt2_lt1_cry # !un2_cnt2_cry_6_) # !C3L1 & !un2_cnt2_cry_6_ & led_un1_cnt2_lt1_cry;

--led_un1_cnt2_lt2_cry is led_un1_cnt2_lt2_cry at LC7_F5
--operation mode is arithmetic

led_un1_cnt2_lt2_cry = CARRY(C3L1 & (led_un1_cnt2_lt1_cry # !un2_cnt2_cry_6_) # !C3L1 & !un2_cnt2_cry_6_ & led_un1_cnt2_lt1_cry);


--A1L512 is led_un1_cnt2_lt1_cry~1 at LC6_F5
--operation mode is arithmetic

A1L512 = C2L1 & (led_un1_cnt2_lt0_cry # !un2_cnt2_cry_7_) # !C2L1 & !un2_cnt2_cry_7_ & led_un1_cnt2_lt0_cry;

--led_un1_cnt2_lt1_cry is led_un1_cnt2_lt1_cry at LC6_F5
--operation mode is arithmetic

led_un1_cnt2_lt1_cry = CARRY(C2L1 & (led_un1_cnt2_lt0_cry # !un2_cnt2_cry_7_) # !C2L1 & !un2_cnt2_cry_7_ & led_un1_cnt2_lt0_cry);


--A1L443 is un6_cnt3_cry_14_~2 at LC5_F14
--operation mode is arithmetic

A1L443 = led_cnt3_18_ $ A1L843;

--un6_cnt3_cry_14_ is un6_cnt3_cry_14_ at LC5_F14
--operation mode is arithmetic

un6_cnt3_cry_14_ = CARRY(led_cnt3_18_ $ A1L843);


--A1L243 is un6_cnt3_cry_13_~2 at LC5_F13
--operation mode is arithmetic

A1L243 = led_cnt3_19_ $ (led_cnt3_18_ & A1L643);

--un6_cnt3_cry_13_ is un6_cnt3_cry_13_ at LC5_F13
--operation mode is arithmetic

un6_cnt3_cry_13_ = CARRY(led_cnt3_19_ $ (led_cnt3_18_ & A1L643));


--A1L043 is un2_cnt2_cry_8_~4 at LC4_F4
--operation mode is arithmetic

A1L043 = led_cnt2_1_ & led_cnt2_0_;

--un2_cnt2_cry_8_ is un2_cnt2_cry_8_ at LC4_F4
--operation mode is arithmetic

un2_cnt2_cry_8_ = CARRY(led_cnt2_1_ & led_cnt2_0_);


--A1L083 is un6_cnt3_cry_32_~4 at LC4_F12
--operation mode is arithmetic

A1L083 = led_cnt3_1_ & led_cnt3_0_;

--un6_cnt3_cry_32_ is un6_cnt3_cry_32_ at LC4_F12
--operation mode is arithmetic

un6_cnt3_cry_32_ = CARRY(led_cnt3_1_ & led_cnt3_0_);


--A1L312 is led_un1_cnt2_lt0_cry~1 at LC5_F5
--operation mode is arithmetic

A1L312 = led_cnt2_0_ & C1L1;

--led_un1_cnt2_lt0_cry is led_un1_cnt2_lt0_cry at LC5_F5
--operation mode is arithmetic

led_un1_cnt2_lt0_cry = CARRY(led_cnt2_0_ & C1L1);


--led_aaaa_0_ is led_aaaa_0_ at LC1_F3
--operation mode is normal

led_aaaa_0__lut_out = led_cnt1_0_ & (led_aaaa_0_ # !led_cnt1_1_) # !led_cnt1_0_ & led_cnt1_1_;
led_aaaa_0_ = DFFEA(led_aaaa_0__lut_out, !GLOBAL(mclk), , , un1_cnt3_2_0, , );


--led_aaaa_1_ is led_aaaa_1_ at LC8_F2
--operation mode is normal

led_aaaa_1__lut_out = led_cnt1_1_ & led_aaaa_1_ # !led_cnt1_0_;
led_aaaa_1_ = DFFEA(led_aaaa_1__lut_out, !GLOBAL(mclk), , , un1_cnt3_2_0, , );


--led_aaaa_2_ is led_aaaa_2_ at LC1_F2
--operation mode is normal

led_aaaa_2__lut_out = led_cnt1_0_ & led_aaaa_2_ # !led_cnt1_1_;
led_aaaa_2_ = DFFEA(led_aaaa_2__lut_out, !GLOBAL(mclk), , , un1_cnt3_2_0, , );


--G_353 is G_353 at LC1_F17
--operation mode is normal

G_353 = !address[2] & !address[1];


--un1_wr_3_0_and2_0_and2 is un1_wr_3_0_and2_0_and2 at LC8_H25
--operation mode is normal

un1_wr_3_0_and2_0_and2 = !cs & !wr & A1L96;


--un1_wr_6_0_and2_0_and2 is un1_wr_6_0_and2_0_and2 at LC6_F8
--operation mode is normal

un1_wr_6_0_and2_0_and2 = !cs & !wr & A1L223 & address[0];


--C9L1 is lpm_latch:iop1_0_|q[0]~1 at LC7_H5
--operation mode is normal

C9L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_0_ # !un1_wr_3_0_and2_0_and2 & C9L1);


--C01L1 is lpm_latch:iop1_1_|q[0]~1 at LC3_I15
--operation mode is normal

C01L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_1_ # !un1_wr_3_0_and2_0_and2 & C01L1);


--C11L1 is lpm_latch:iop1_2_|q[0]~1 at LC7_I15
--operation mode is normal

C11L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_2_ # !un1_wr_3_0_and2_0_and2 & C11L1);


--C21L1 is lpm_latch:iop1_3_|q[0]~1 at LC3_J3
--operation mode is normal

C21L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_3_ # !un1_wr_3_0_and2_0_and2 & C21L1);


--C31L1 is lpm_latch:iop1_4_|q[0]~1 at LC7_H21
--operation mode is normal

C31L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_4_ # !un1_wr_3_0_and2_0_and2 & C31L1);


--C41L1 is lpm_latch:iop1_5_|q[0]~1 at LC2_I36
--operation mode is normal

C41L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_5_ # !un1_wr_3_0_and2_0_and2 & C41L1);


--C51L1 is lpm_latch:iop1_6_|q[0]~1 at LC1_F35
--operation mode is normal

C51L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_6_ # !un1_wr_3_0_and2_0_and2 & C51L1);


--C61L1 is lpm_latch:iop1_7_|q[0]~1 at LC2_F33
--operation mode is normal

C61L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_7_ # !un1_wr_3_0_and2_0_and2 & C61L1);


--C71L1 is lpm_latch:iop1_8_|q[0]~1 at LC3_J34
--operation mode is normal

C71L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_8_ # !un1_wr_3_0_and2_0_and2 & C71L1);


--C81L1 is lpm_latch:iop1_9_|q[0]~1 at LC6_J31
--operation mode is normal

C81L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_9_ # !un1_wr_3_0_and2_0_and2 & C81L1);


--C91L1 is lpm_latch:iop1_10_|q[0]~1 at LC2_I31
--operation mode is normal

C91L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_10_ # !un1_wr_3_0_and2_0_and2 & C91L1);


--C02L1 is lpm_latch:iop1_11_|q[0]~1 at LC2_H30
--operation mode is normal

C02L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_11_ # !un1_wr_3_0_and2_0_and2 & C02L1);


--C12L1 is lpm_latch:iop1_12_|q[0]~1 at LC3_I29
--operation mode is normal

C12L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_12_ # !un1_wr_3_0_and2_0_and2 & C12L1);


--C22L1 is lpm_latch:iop1_13_|q[0]~1 at LC4_H28
--operation mode is normal

C22L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_13_ # !un1_wr_3_0_and2_0_and2 & C22L1);


--C32L1 is lpm_latch:iop1_14_|q[0]~1 at LC3_H26
--operation mode is normal

C32L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_14_ # !un1_wr_3_0_and2_0_and2 & C32L1);


--C42L1 is lpm_latch:iop1_15_|q[0]~1 at LC7_H25
--operation mode is normal

C42L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_3_0_and2_0_and2 & data_15_ # !un1_wr_3_0_and2_0_and2 & C42L1);


--G_352 is G_352 at LC2_F8
--operation mode is normal

G_352 = !address[3] & !address[4] & G_350_lc;


--un1_wr_4_0_and2_0_and2 is un1_wr_4_0_and2_0_and2 at LC7_H26
--operation mode is normal

un1_wr_4_0_and2_0_and2 = !cs & !wr & A1L07;


--C52L1 is lpm_latch:iop1_16_|q[0]~1 at LC1_F26
--operation mode is normal

C52L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_0_ # !un1_wr_4_0_and2_0_and2 & C52L1);


--C62L1 is lpm_latch:iop1_17_|q[0]~1 at LC1_H23
--operation mode is normal

C62L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_1_ # !un1_wr_4_0_and2_0_and2 & C62L1);


--C72L1 is lpm_latch:iop1_18_|q[0]~1 at LC2_H23
--operation mode is normal

C72L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_2_ # !un1_wr_4_0_and2_0_and2 & C72L1);


--C82L1 is lpm_latch:iop1_19_|q[0]~1 at LC2_H21
--operation mode is normal

C82L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_3_ # !un1_wr_4_0_and2_0_and2 & C82L1);


--C92L1 is lpm_latch:iop1_20_|q[0]~1 at LC5_H21
--operation mode is normal

C92L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_4_ # !un1_wr_4_0_and2_0_and2 & C92L1);


--C03L1 is lpm_latch:iop1_21_|q[0]~1 at LC5_H19
--operation mode is normal

C03L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_5_ # !un1_wr_4_0_and2_0_and2 & C03L1);


--C13L1 is lpm_latch:iop1_22_|q[0]~1 at LC1_H19
--operation mode is normal

C13L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_6_ # !un1_wr_4_0_and2_0_and2 & C13L1);


--C23L1 is lpm_latch:iop1_23_|q[0]~1 at LC2_H19
--operation mode is normal

C23L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_7_ # !un1_wr_4_0_and2_0_and2 & C23L1);


--C33L1 is lpm_latch:iop1_24_|q[0]~1 at LC2_F18
--operation mode is normal

C33L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_8_ # !un1_wr_4_0_and2_0_and2 & C33L1);


--C43L1 is lpm_latch:iop1_25_|q[0]~1 at LC4_I15
--operation mode is normal

C43L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_9_ # !un1_wr_4_0_and2_0_and2 & C43L1);


--C53L1 is lpm_latch:iop1_26_|q[0]~1 at LC2_I15
--operation mode is normal

C53L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_10_ # !un1_wr_4_0_and2_0_and2 & C53L1);


--C63L1 is lpm_latch:iop1_27_|q[0]~1 at LC2_H14
--operation mode is normal

C63L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_11_ # !un1_wr_4_0_and2_0_and2 & C63L1);


--C73L1 is lpm_latch:iop1_28_|q[0]~1 at LC5_H14
--operation mode is normal

C73L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_12_ # !un1_wr_4_0_and2_0_and2 & C73L1);


--C83L1 is lpm_latch:iop1_29_|q[0]~1 at LC8_H14
--operation mode is normal

C83L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_13_ # !un1_wr_4_0_and2_0_and2 & C83L1);


--C93L1 is lpm_latch:iop1_30_|q[0]~1 at LC6_H11
--operation mode is normal

C93L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_14_ # !un1_wr_4_0_and2_0_and2 & C93L1);


--C04L1 is lpm_latch:iop1_31_|q[0]~1 at LC2_H11
--operation mode is normal

C04L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_4_0_and2_0_and2 & data_15_ # !un1_wr_4_0_and2_0_and2 & C04L1);


--G_366 is G_366 at LC4_F18
--operation mode is normal

G_366 = address[1] & !address[2] & G_356_lc;


--un1_wr_7_0_and2_0_and2 is un1_wr_7_0_and2_0_and2 at LC2_H25
--operation mode is normal

un1_wr_7_0_and2_0_and2 = !cs & !wr & G_366;


--C14L1 is lpm_latch:iop2_0_|q[0]~1 at LC6_H28
--operation mode is normal

C14L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_0_ # !un1_wr_7_0_and2_0_and2 & C14L1);


--C24L1 is lpm_latch:iop2_1_|q[0]~1 at LC1_H28
--operation mode is normal

C24L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_1_ # !un1_wr_7_0_and2_0_and2 & C24L1);


--C34L1 is lpm_latch:iop2_2_|q[0]~1 at LC6_H30
--operation mode is normal

C34L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_2_ # !un1_wr_7_0_and2_0_and2 & C34L1);


--C44L1 is lpm_latch:iop2_3_|q[0]~1 at LC4_H30
--operation mode is normal

C44L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_3_ # !un1_wr_7_0_and2_0_and2 & C44L1);


--C54L1 is lpm_latch:iop2_4_|q[0]~1 at LC2_F32
--operation mode is normal

C54L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_4_ # !un1_wr_7_0_and2_0_and2 & C54L1);


--C64L1 is lpm_latch:iop2_5_|q[0]~1 at LC1_F32
--operation mode is normal

C64L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_5_ # !un1_wr_7_0_and2_0_and2 & C64L1);


--C74L1 is lpm_latch:iop2_6_|q[0]~1 at LC6_H34
--operation mode is normal

C74L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_6_ # !un1_wr_7_0_and2_0_and2 & C74L1);


--C84L1 is lpm_latch:iop2_7_|q[0]~1 at LC3_H34
--operation mode is normal

C84L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_7_ # !un1_wr_7_0_and2_0_and2 & C84L1);


--C94L1 is lpm_latch:iop2_8_|q[0]~1 at LC1_J34
--operation mode is normal

C94L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_8_ # !un1_wr_7_0_and2_0_and2 & C94L1);


--C05L1 is lpm_latch:iop2_9_|q[0]~1 at LC4_I36
--operation mode is normal

C05L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_9_ # !un1_wr_7_0_and2_0_and2 & C05L1);


--C15L1 is lpm_latch:iop2_10_|q[0]~1 at LC1_I36
--operation mode is normal

C15L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_10_ # !un1_wr_7_0_and2_0_and2 & C15L1);


--C25L1 is lpm_latch:iop2_11_|q[0]~1 at LC1_H30
--operation mode is normal

C25L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_11_ # !un1_wr_7_0_and2_0_and2 & C25L1);


--C35L1 is lpm_latch:iop2_12_|q[0]~1 at LC5_I29
--operation mode is normal

C35L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_12_ # !un1_wr_7_0_and2_0_and2 & C35L1);


--C45L1 is lpm_latch:iop2_13_|q[0]~1 at LC8_H30
--operation mode is normal

C45L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_13_ # !un1_wr_7_0_and2_0_and2 & C45L1);


--C55L1 is lpm_latch:iop2_14_|q[0]~1 at LC1_H26
--operation mode is normal

C55L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_14_ # !un1_wr_7_0_and2_0_and2 & C55L1);


--C65L1 is lpm_latch:iop2_15_|q[0]~1 at LC5_H25
--operation mode is normal

C65L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_7_0_and2_0_and2 & data_15_ # !un1_wr_7_0_and2_0_and2 & C65L1);


--G_369 is G_369 at LC2_F17
--operation mode is normal

G_369 = address[1] & !address[2] & address[0] & G_352;


--un1_wr_5_0_and2_0_and2 is un1_wr_5_0_and2_0_and2 at LC6_H25
--operation mode is normal

un1_wr_5_0_and2_0_and2 = !cs & !wr & G_369;


--C75L1 is lpm_latch:iop2_16_|q[0]~1 at LC8_H5
--operation mode is normal

C75L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_0_ # !un1_wr_5_0_and2_0_and2 & C75L1);


--C85L1 is lpm_latch:iop2_17_|q[0]~1 at LC1_I15
--operation mode is normal

C85L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_1_ # !un1_wr_5_0_and2_0_and2 & C85L1);


--C95L1 is lpm_latch:iop2_18_|q[0]~1 at LC5_I15
--operation mode is normal

C95L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_2_ # !un1_wr_5_0_and2_0_and2 & C95L1);


--C06L1 is lpm_latch:iop2_19_|q[0]~1 at LC8_H21
--operation mode is normal

C06L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_3_ # !un1_wr_5_0_and2_0_and2 & C06L1);


--C16L1 is lpm_latch:iop2_20_|q[0]~1 at LC1_H21
--operation mode is normal

C16L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_4_ # !un1_wr_5_0_and2_0_and2 & C16L1);


--C26L1 is lpm_latch:iop2_21_|q[0]~1 at LC3_H21
--operation mode is normal

C26L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_5_ # !un1_wr_5_0_and2_0_and2 & C26L1);


--C36L1 is lpm_latch:iop2_22_|q[0]~1 at LC5_H30
--operation mode is normal

C36L1 = !un1_wr_6_0_and2_0_and2 & (un1_wr_5_0_and2_0_and2 & data_6_ # !un1_wr_5_0_and2_0_and2 & C36L1);


--C46L1 is lpm_latch:iop2_23_|q[0]~1 at LC8_H34
--operation mode is normal