armexio.srr

usoc在北京博创兴业有限公司的实验平台s3c2410上运行。 2. 各实验的全部源代码分别存放在各实验目录下面。

$ Start of Compile
#Mon Nov 24 10:24:30 2003

Synplicity VHDL Compiler, version Compilers 7.3, Build 073R, built May 30 2003
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

@N:"E:\Exp23_1\FPGA\armExIO.vhd":47:7:47:13|Top entity is set to armExIO.
VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

Synthesizing work.armexio.armexio
@W:"E:\Exp23_1\FPGA\armExIO.vhd":84:7:84:13|Incomplete sensitivity list - assuming completeness
@W:"E:\Exp23_1\FPGA\armExIO.vhd":89:25:89:28|Referenced variable data is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":87:8:87:14|Referenced variable address is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":111:6:111:12|Incomplete sensitivity list - assuming completeness
@W:"E:\Exp23_1\FPGA\armExIO.vhd":130:22:130:25|Referenced variable cnt4 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":122:11:122:14|Referenced variable iop2 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":118:11:118:14|Referenced variable iop1 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":126:11:126:14|Referenced variable iop3 is not in sensitivity list
@W:"E:\Exp23_1\FPGA\armExIO.vhd":116:8:116:14|Referenced variable address is not in sensitivity list
Post processing for work.armexio.armexio
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(36) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(32) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(33) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(34) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(35) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop1(36) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop1(36 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(35) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(34) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(33) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|All reachable assignments to iop2(32) assign '0', register removed by optimization
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(31), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(30), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(29), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(28), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(27), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(26), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(25), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(25), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(24), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(24), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(23), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(23), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(22), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(22), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(21), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(21), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(20), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(20), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(19), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(19), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(18), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(18), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(17), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(17), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(16), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(16), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(15), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(15), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(14), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(14), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(13), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(13), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(12), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(12), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(11), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(11), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(10), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(10), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(9), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(9), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(8), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(8), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(7), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(7), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(6), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(6), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(5), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(5), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(4), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(4), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(3), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(3), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(2), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(2), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(1), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(1), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop3(0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal iop2(0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":86:2:86:3|Latch generated from process for signal cnt4(7 downto 0), probably caused by a missing assignment in an if or case stmt
@W:"E:\Exp23_1\FPGA\armExIO.vhd":26:3:26:7|Input reset is unused
@W:"E:\Exp23_1\FPGA\armExIO.vhd":28:3:28:8|Input switch is unused
@W:"E:\Exp23_1\FPGA\armExIO.vhd":29:3:29:8|Input unused is unused
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Altera Technology Mapper, version 7.3, Build 173R, built Jun 10 2003
Copyright (C) 1994-2003, Synplicity Inc.  All Rights Reserved


@W:"e:\exp23_1\fpga\armexio.vhd":61:2:61:3|Removing instance led[1],  because it is equivalent to instance led.aaaa[1]
@W:"e:\exp23_1\fpga\armexio.vhd":61:2:61:3|Removing instance led[0],  because it is equivalent to instance led.aaaa[0]
@W:"e:\exp23_1\fpga\armexio.vhd":61:2:61:3|Removing instance led[2],  because it is equivalent to instance led.aaaa[2]

Writing Analyst data base E:\Exp23_1\FPGA\rev_1\armExIO.srm
Writing EDIF Netlist and constraint files
Found clock armExIO|mclk with period 1000.00ns 
@W:"e:\exp23_1\fpga\armexio.vhd":87:3:87:6|Net un1_wr_7_0_and2_0_and2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\exp23_1\fpga\armexio.vhd":87:3:87:6|Net un1_wr_2_0_and2_0_and2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\exp23_1\fpga\armexio.vhd":87:3:87:6|Net un1_wr_1_0_and2_0_and2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\exp23_1\fpga\armexio.vhd":87:3:87:6|Net un1_wr_5_0_and2_0_and2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\exp23_1\fpga\armexio.vhd":87:3:87:6|Net un1_wr_4_0_and2_0_and2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\exp23_1\fpga\armexio.vhd":87:3:87:6|Net un1_wr_3_0_and2_0_and2 appears to be a clock source which was not identified. Assuming default frequency. 
@W:"e:\exp23_1\fpga\armexio.vhd":87:3:87:6|Net un1_wr_8_0_and2_0_and2 appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Nov 24 10:24:36 2003
#


Top view:               armExIO
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.

@N| Clock constraints cover only FF-to-FF paths associated with the clock.



Performance Summary 
*******************


Worst slack in design: 984.356

                   Requested     Estimated     Requested     Estimated                 Clock        Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type         Group           
--------------------------------------------------------------------------------------------------------------------
armExIO|mclk       1.0 MHz       63.9 MHz      1000.000      15.644        984.356     inferred     default_clkgroup
System             1.0 MHz       92.0 MHz      1000.000      10.874        989.126     system       default_clkgroup
====================================================================================================================





Clock Relationships
*******************

Clocks                      |    rise  to  rise   |    fall  to  fall     |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------------------
Starting      Ending        |  constraint  slack  |  constraint  slack    |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------------------
armExIO|mclk  armExIO|mclk  |  No paths    -      |  1000.000    984.356  |  No paths    -      |  No paths    -    
====================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: armExIO|mclk
====================================



Starting Points with Worst Slack
********************************

                 Starting                                             Arrival            
Instance         Reference        Type       Pin     Net              Time        Slack  
                 Clock                                                                   
-----------------------------------------------------------------------------------------
led.cnt3[15]     armExIO|mclk     S_DFF      Q       led.cnt3[15]     2.500       984.356
led.cnt3[10]     armExIO|mclk     S_DFF      Q       led.cnt3[10]     2.140       984.516
led.cnt3[11]     armExIO|mclk     S_DFF      Q       led.cnt3[11]     2.140       984.516
led.cnt2[0]      armExIO|mclk     S_DFFE     Q       led.cnt2[0]      2.500       985.786
led.cnt2[1]      armExIO|mclk     S_DFFE     Q       led.cnt2[1]      2.140       986.146
led.cnt3[6]      armExIO|mclk     S_DFF      Q       led.cnt3[6]      2.140       986.366
led.cnt3[7]      armExIO|mclk     S_DFF      Q       led.cnt3[7]      2.140       986.366
led.cnt3[8]      armExIO|mclk     S_DFF      Q       led.cnt3[8]      2.140       986.366
led.cnt3[12]     armExIO|mclk     S_DFF      Q       led.cnt3[12]     2.140       986.366
led.cnt3[13]     armExIO|mclk     S_DFF      Q       led.cnt3[13]     2.140       986.366