armexio.map.rpt

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Analysis & Synthesis report for armExIO compilation.
Mon Nov 24 10:24:58 2003
Version 3.0 Build 199 06/26/2003 SJ Full Version

Command: quartus_map --import_settings_files=on --export_settings_files=off armExIO -c armExIO



---------------------
; Table of Contents ;
---------------------
   1. Legal Notice
   2. Flow Summary
   3. Flow Settings
   4. Flow Elapsed Time
   5. Analysis & Synthesis Summary
   6. Analysis & Synthesis Settings
   7. Hierarchy
   8. Analysis & Synthesis Resource Utilization by Entity
   9. Analysis & Synthesis Equations
  10. Analysis & Synthesis Messages


----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2003 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.



-----------------------------------------------------------------
; Flow Summary                                                  ;
-----------------------------------------------------------------
; Flow Status           ; Successful - Mon Nov 24 10:24:58 2003 ;
; Compiler Setting Name ; armExIO                               ;
; Top-level Entity Name ; armExIO                               ;
; Family                ; ACEX1K                                ;
; Device                ; EP1K50QC208-3                         ;
; Total logic elements  ; 270                                   ;
; Total pins            ; 144                                   ;
; Total memory bits     ; 0                                     ;
; Total PLLs            ; 0                                     ;
-----------------------------------------------------------------


-----------------------------------------------
; Flow Settings                               ;
-----------------------------------------------
; Option                ; Setting             ;
-----------------------------------------------
; Start date & time     ; 11/24/2003 10:24:54 ;
; Main task             ; Compilation         ;
; Compiler Setting Name ; armExIO             ;
-----------------------------------------------


---------------------------------------
; Flow Elapsed Time                   ;
---------------------------------------
; Module Name          ; Elapsed Time ;
---------------------------------------
; Analysis & Synthesis ; 00:00:04     ;
; Total                ; 00:00:04     ;
---------------------------------------


-----------------------------------------------------------------------
; Analysis & Synthesis Summary                                        ;
-----------------------------------------------------------------------
; Analysis & Synthesis Status ; Successful - Mon Nov 24 10:24:58 2003 ;
; Compiler Setting Name       ; armExIO                               ;
; Top-level Entity Name       ; armExIO                               ;
; Family                      ; ACEX1K                                ;
; Total logic elements        ; 270                                   ;
; Total pins                  ; 144                                   ;
; Total memory bits           ; 0                                     ;
; Total PLLs                  ; 0                                     ;
-----------------------------------------------------------------------


------------------------------------------------------------
; Analysis & Synthesis Settings                            ;
------------------------------------------------------------
; Option                                        ; Setting  ;
------------------------------------------------------------
; Use Generated Physical Constraints File       ; On       ;
; Physical Synthesis Level for Resynthesis      ; Normal   ;
; Resynthesis Optimization Effort               ; Normal   ;
; Type of Retiming Performed During Resynthesis ; Full     ;
; Focus entity name                             ; |armExIO ;
; Family name                                   ; ACEX1K   ;
; Preserve fewer node names                     ; On       ;
; Disk space/compilation speed tradeoff         ; Normal   ;
------------------------------------------------------------


--------------
; Hierarchy  ;
--------------
Hierarchy
  armExIO
    L2_2:cnt3_3_0_and2_L_18_
    L2_2:cnt3_3_0_and2_L_19_
    lpm_latch:cnt4_0_
    lpm_latch:cnt4_1_
    lpm_latch:cnt4_2_
    lpm_latch:cnt4_3_
    lpm_latch:cnt4_4_
    lpm_latch:cnt4_5_
    lpm_latch:cnt4_6_
    lpm_latch:cnt4_7_
    lpm_latch:iop1_0_
    lpm_latch:iop1_1_
    lpm_latch:iop1_2_
    lpm_latch:iop1_3_
    lpm_latch:iop1_4_
    lpm_latch:iop1_5_
    lpm_latch:iop1_6_
    lpm_latch:iop1_7_
    lpm_latch:iop1_8_
    lpm_latch:iop1_9_
    lpm_latch:iop1_10_
    lpm_latch:iop1_11_
    lpm_latch:iop1_12_
    lpm_latch:iop1_13_
    lpm_latch:iop1_14_
    lpm_latch:iop1_15_
    lpm_latch:iop1_16_
    lpm_latch:iop1_17_
    lpm_latch:iop1_18_
    lpm_latch:iop1_19_
    lpm_latch:iop1_20_
    lpm_latch:iop1_21_
    lpm_latch:iop1_22_
    lpm_latch:iop1_23_
    lpm_latch:iop1_24_
    lpm_latch:iop1_25_
    lpm_latch:iop1_26_
    lpm_latch:iop1_27_
    lpm_latch:iop1_28_
    lpm_latch:iop1_29_
    lpm_latch:iop1_30_
    lpm_latch:iop1_31_
    lpm_latch:iop2_0_
    lpm_latch:iop2_1_
    lpm_latch:iop2_2_
    lpm_latch:iop2_3_
    lpm_latch:iop2_4_
    lpm_latch:iop2_5_
    lpm_latch:iop2_6_
    lpm_latch:iop2_7_
    lpm_latch:iop2_8_
    lpm_latch:iop2_9_
    lpm_latch:iop2_10_
    lpm_latch:iop2_11_
    lpm_latch:iop2_12_
    lpm_latch:iop2_13_
    lpm_latch:iop2_14_
    lpm_latch:iop2_15_
    lpm_latch:iop2_16_
    lpm_latch:iop2_17_
    lpm_latch:iop2_18_
    lpm_latch:iop2_19_
    lpm_latch:iop2_20_
    lpm_latch:iop2_21_
    lpm_latch:iop2_22_
    lpm_latch:iop2_23_
    lpm_latch:iop2_24_
    lpm_latch:iop2_25_
    lpm_latch:iop2_26_
    lpm_latch:iop2_27_
    lpm_latch:iop2_28_
    lpm_latch:iop2_29_
    lpm_latch:iop2_30_
    lpm_latch:iop2_31_
    lpm_latch:iop3_0_
    lpm_latch:iop3_1_
    lpm_latch:iop3_2_
    lpm_latch:iop3_3_
    lpm_latch:iop3_4_
    lpm_latch:iop3_5_
    lpm_latch:iop3_6_
    lpm_latch:iop3_7_
    lpm_latch:iop3_8_
    lpm_latch:iop3_9_
    lpm_latch:iop3_10_
    lpm_latch:iop3_11_
    lpm_latch:iop3_12_
    lpm_latch:iop3_13_
    lpm_latch:iop3_14_