📄 io.h
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/***************************************************************************\
Copyright (c) 2004-2007 threewater@up-tech.com, All rights reserved.
by threewter 2004.4.26
\***************************************************************************/
/***************************************************************************\
#说明: 标准输入输出函数
---------------------------------- Bug --------------------------------------
---------------------------------- TODO list --------------------------------------
----------------------------------修正--------------------------------------
2004-4-26 创建
\***************************************************************************/
#ifndef __IO_H__
#define __IO_H__
#define _outb(addr, data) *((volatile unsigned char*)(addr))=(data)
#define _outw(addr, data) *((volatile unsigned short*)(addr))=(data)
#define _outl(addr, data) *((volatile unsigned long*)(addr))=(data)
#define _inb(addr) (*(volatile unsigned char*)(addr))
#define _inw(addr) (*(volatile unsigned short*)(addr))
#define _inl(addr) (*(volatile unsigned long*)(addr))
/***********************************************************************************/
#define rDISRC2 (*(volatile unsigned *)0x4B000080)
#define rDISRCC2 (*(volatile unsigned *)0x4B000084)
#define rDIDST2 (*(volatile unsigned *)0x4B000088)
#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
#define rDCON2 (*(volatile unsigned *)0x4B000090)
#define rDSTAT2 (*(volatile unsigned *)0x4B000094)
#define rDCSRC2 (*(volatile unsigned *)0x4B000098)
#define rDCDST2 (*(volatile unsigned *)0x4B00009C)
#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
/* IIS */
#define rIISCON (*(volatile unsigned *)0x55000000)
#define rIISMOD (*(volatile unsigned *)0x55000004)
#define rIISPSR (*(volatile unsigned *)0x55000008)
#define rIISFCON (*(volatile unsigned short *)0x5500000c)
#define rIISFIF (*(volatile unsigned short *)0x55000010)
#define IISCON_RIGHT_INDEX 0x100 //Right Channel
#define IISCON_TXFIFO_NE 0x80 //Transmit FIFO not empty flag
#define IISCON_RXFIFO_NE 0x40 //Transmit FIFO not empty flag
#define IISCON_TXDMA 0x20 //Transmit DMA service request enable
#define IISCON_RXDMA 0x10 //Receive DMA service request enable
#define IISCON_TXIDLE 0x08 //Transmit channel idle
#define IISCON_RXIDLE 0x04 //Receive channel idle
#define IISCON_PRESCALE 0x02 //IIS prescaler enable
#define IISCON_ENABLE 0x01 //IIS interface enable(start)
#define IISMOD_SLAVE 0x100 //slave mode select
#define IISMOD_TX 0x80 //Transmit mode
#define IISMOD_RX 0x40 //receive mode
#define IISMOD_RACTIVE 0x20 //Active level of right
#define IISMOD_MSBJ 0x10 //MSB-justified Serial interface format
#define IISMOD_16BIT 0x08 //Serial data 16bit per channel
#define IISMOD_MCLK_384FS 0x04 //Master clock frequency
#define IISMOD_32FS 0x01 //Serial bit clock frequency=32fs
#define IISMOD_48FS 0x02 //Serial bit clock frequency=48fs
#define IISFCON_TXDMA 0x800 //Transmit FIFO access DMA mode
#define IISFCON_RXDMA 0x400 //Receive FIFO access DMA mode
#define IISFCON_TXFIFO 0x200 //Transmit FIFO enable
#define IISFCON_RXFIFO 0x100 //Receive FIFO enable
#define DEF_VOLUME 100
/* UDA1341 Register bits */
#define UDA1341_ADDR 0x14
#define UDA1341_REG_DATA0 (UDA1341_ADDR + 0)
#define UDA1341_REG_STATUS (UDA1341_ADDR + 2)
/* status control */
#define STAT0 (0x00)
#define STAT0_RST (1 << 6)
#define STAT0_SC_MASK (3 << 4)
#define STAT0_SC_512FS (0 << 4)
#define STAT0_SC_384FS (1 << 4)
#define STAT0_SC_256FS (2 << 4)
#define STAT0_IF_MASK (7 << 1)
#define STAT0_IF_I2S (0 << 1)
#define STAT0_IF_LSB16 (1 << 1)
#define STAT0_IF_LSB18 (2 << 1)
#define STAT0_IF_LSB20 (3 << 1)
#define STAT0_IF_MSB (4 << 1)
#define STAT0_IF_LSB16MSB (5 << 1)
#define STAT0_IF_LSB18MSB (6 << 1)
#define STAT0_IF_LSB20MSB (7 << 1)
#define STAT0_DC_FILTER (1 << 0)
#define STAT0_DC_NO_FILTER (0 << 0)
#define STAT1 (0x80)
#define STAT1_DAC_GAIN (1 << 6) /* gain of DAC */
#define STAT1_ADC_GAIN (1 << 5) /* gain of ADC */
#define STAT1_ADC_POL (1 << 4) /* polarity of ADC */
#define STAT1_DAC_POL (1 << 3) /* polarity of DAC */
#define STAT1_DBL_SPD (1 << 2) /* double speed playback */
#define STAT1_ADC_ON (1 << 1) /* ADC powered */
#define STAT1_DAC_ON (1 << 0) /* DAC powered */
/* data0 direct control */
#define DATA0 (0x00)
#define DATA0_VOLUME_MASK (0x3f)
#define DATA0_VOLUME(x) (x)
#define DATA1 (0x40)
#define DATA1_BASS(x) ((x) << 2)
#define DATA1_BASS_MASK (15 << 2)
#define DATA1_TREBLE(x) ((x))
#define DATA1_TREBLE_MASK (3)
#define DATA2 (0x80)
#define DATA2_PEAKAFTER (0x1 << 5)
#define DATA2_DEEMP_NONE (0x0 << 3)
#define DATA2_DEEMP_32KHz (0x1 << 3)
#define DATA2_DEEMP_44KHz (0x2 << 3)
#define DATA2_DEEMP_48KHz (0x3 << 3)
#define DATA2_MUTE (0x1 << 2)
#define DATA2_FILTER_FLAT (0x0 << 0)
#define DATA2_FILTER_MIN (0x1 << 0)
#define DATA2_FILTER_MAX (0x3 << 0)
/* data0 extend control */
#define EXTADDR(n) (0xc0 | (n))
#define EXTDATA(d) (0xe0 | (d))
#define EXT0 0
#define EXT0_CH1_GAIN(x) (x)
#define EXT1 1
#define EXT1_CH2_GAIN(x) (x)
#define EXT2 2
#define EXT2_MIC_GAIN_MASK (7 << 2)
#define EXT2_MIC_GAIN(x) ((x) << 2)
#define EXT2_MIXMODE_DOUBLEDIFF (0)
#define EXT2_MIXMODE_CH1 (1)
#define EXT2_MIXMODE_CH2 (2)
#define EXT2_MIXMODE_MIX (3)
#define EXT4 4
#define EXT4_AGC_ENABLE (1 << 4)
#define EXT4_INPUT_GAIN_MASK (3)
#define EXT4_INPUT_GAIN(x) ((x) & 3)
#define EXT5 5
#define EXT5_INPUT_GAIN(x) ((x) >> 2)
#define EXT6 6
#define EXT6_AGC_CONSTANT_MASK (7 << 2)
#define EXT6_AGC_CONSTANT(x) ((x) << 2)
#define EXT6_AGC_LEVEL_MASK (3)
#define EXT6_AGC_LEVEL(x) (x)
#define AUDIO_CLK 44100 //44.1KHz的音频时钟
#define AUDIO_BIT 16 //16位音频
#define AUDIO_OUT_BUFFERSIZE (AUDIO_CLK/2) //500ms的缓冲区
#define AUDIO_IN_BUFFERSIZE (AUDIO_CLK/2) //500ms的缓冲区
#define AUDIO_OUT_BUFFERSIZE_B (AUDIO_OUT_BUFFERSIZE*4)
#define AUDIO_IN_BUFFERSIZE_B (AUDIO_IN_BUFFERSIZE*4)
///////////////////////////UDA1341/////////////////////////////////////////////////
#define UDA1341_MODE (1<<8)
#define UDAADDR 0x14 //UDA1341 address
#define UDA_DATA0 0x00 //UDA1341 data0
#define UDA_DATA1 0x01 //UDA1341 data1
#define UDA_STATUS 0x02 //UDA1341 status
#define UDASTATUS0_RST 0x40 //UDA1341 status reset
#define UDASTATUS0_SC512 0x00 //UDA1341 status SC
#define UDASTATUS0_SC384 0x10 //UDA1341 status SC
#define UDASTATUS0_SC256 0x20 //UDA1341 status SC
#define UDASTATUS0_IIS 0x00 //UDA1341 status IF2-0=0 IIS
#define UDASTATUS0_DC 0x01 //UDA1341 status DC-filtering
#define UDASTATUS1_OGS6 (0x80|0x40) //UDA1341 status gain of DAC 6dB
#define UDASTATUS1_IGS6 (0x80|0x20) //UDA1341 status gain of ADC 6dB
#define UDASTATUS1_PADINV (0x80|0x10) //UDA1341 status ADC inverting
#define UDASTATUS1_PDAINV (0x80|0x08) //UDA1341 status DAC inverting
#define UDASTATUS1_DBSPD (0x80|0x04) //UDA1341 status double speed
#define UDASTATUS1_ADCON (0x80|0x02) //UDA1341 status ADC on
#define UDASTATUS1_DACON (0x80|0x01) //UDA1341 status DAC on
#define UDADATA0_VOL 0x00 //UDA1341 data0 volume value 6bit
#define L3CLK (1<<9)
#define L3DATA (1<<10)
#define GPIO_L3CLOCK (GPIO_MODE_OUT | GPIO_PULLUP_DIS | GPIO_G9)
#define GPIO_L3DATA (GPIO_MODE_OUT | GPIO_PULLUP_DIS | GPIO_G10)
#define GPIO_L3MODE (GPIO_MODE_OUT | GPIO_PULLUP_DIS | GPIO_G8)
#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
#define rIISCON (*(volatile unsigned *)0x55000000)
/****************************************************************************************/
#endif
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