📄 cmd_usb_down.c.svn-base
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// EP3: bulk out end point
// EP4: not used
rPWR_REG = PWR_REG_DEFAULT_VALUE; //disable suspend mode
rINDEX_REG = 0;
rMAXP_REG = FIFO_SIZE_8; //EP0 max packit size = 8
rEP0_CSR = EP0_SERVICED_OUT_PKT_RDY|EP0_SERVICED_SETUP_END;
rINDEX_REG = 1; //EP0:clear OUT_PKT_RDY & SETUP_END
rMAXP_REG = FIFO_SIZE_64; //EP1:max packit size = 64
rIN_CSR1_REG = EPI_FIFO_FLUSH|EPI_CDT;
rIN_CSR2_REG = EPI_MODE_IN|EPI_IN_DMA_INT_MASK|EPI_BULK; //IN mode, IN_DMA_INT=masked
rOUT_CSR1_REG = EPO_CDT;
rOUT_CSR2_REG = EPO_BULK|EPO_OUT_DMA_INT_MASK;
rINDEX_REG = 2;
rMAXP_REG = FIFO_SIZE_64; //EP2:max packit size = 64
rIN_CSR1_REG = EPI_FIFO_FLUSH|EPI_CDT|EPI_BULK;
rIN_CSR2_REG = EPI_MODE_IN|EPI_IN_DMA_INT_MASK; //IN mode, IN_DMA_INT=masked
rOUT_CSR1_REG = EPO_CDT;
rOUT_CSR2_REG = EPO_BULK|EPO_OUT_DMA_INT_MASK;
rINDEX_REG = 3;
rMAXP_REG = FIFO_SIZE_64; //EP3:max packit size = 64
rIN_CSR1_REG = EPI_FIFO_FLUSH|EPI_CDT|EPI_BULK;
rIN_CSR2_REG = EPI_MODE_OUT|EPI_IN_DMA_INT_MASK; //OUT mode, IN_DMA_INT=masked
rOUT_CSR1_REG = EPO_CDT;
//clear OUT_PKT_RDY, data_toggle_bit.
//The data toggle bit should be cleared when initialization.
rOUT_CSR2_REG = EPO_BULK|EPO_OUT_DMA_INT_MASK;
rINDEX_REG = 4;
rMAXP_REG = FIFO_SIZE_64; //EP4:max packit size = 64
rIN_CSR1_REG = EPI_FIFO_FLUSH|EPI_CDT|EPI_BULK;
rIN_CSR2_REG = EPI_MODE_OUT|EPI_IN_DMA_INT_MASK; //OUT mode, IN_DMA_INT=masked
rOUT_CSR1_REG = EPO_CDT;
//clear OUT_PKT_RDY, data_toggle_bit.
//The data toggle bit should be cleared when initialization.
rOUT_CSR2_REG = EPO_BULK|EPO_OUT_DMA_INT_MASK;
rEP_INT_REG = EP0_INT|EP1_INT|EP2_INT|EP3_INT|EP4_INT;
rUSB_INT_REG = RESET_INT|SUSPEND_INT|RESUME_INT;
//Clear all usbd pending bits
//EP0,1,3 & reset interrupt are enabled
rEP_INT_EN_REG = EP0_INT|EP1_INT|EP3_INT;
rUSB_INT_EN_REG = RESET_INT;
ep0State = EP0_STATE_INIT;
}
void Clk0_Disable(void)
{
rGPHCON = rGPHCON&~(3<<18); // GPH9 Input
}
void Clk1_Disable(void)
{
rGPHCON = rGPHCON&~(3<<20); // GPH10 Input
}
void RdPktEp0(u8 *buf, int num)
{
int i;
for(i=0;i<num;i++) buf[i]=(u8)rEP0_FIFO;
}
void WrPktEp0(u8 *buf, int num)
{
int i;
for(i=0;i<num;i++) rEP0_FIFO=buf[i];
}
void PrintEp0Pkt(u8 *pt)
{
int i;
dbgprintf("[RCV:");
for(i=0;i<EP0_PKT_SIZE;i++) dbgprintf("%x,",pt[i]);
dbgprintf("]");
}
void Ep0Handler(void)
{
static int ep0SubState;
int i;
u8 ep0_csr;
rINDEX_REG = 0;
ep0_csr = rEP0_CSR;
if(ep0_csr & EP0_SETUP_END)
{
// Host may end GET_DESCRIPTOR operation without completing the IN data stage.
// If host does that, SETUP_END bit will be set.
// OUT_PKT_RDY has to be also cleared because status stage sets OUT_PKT_RDY to 1.
dbgprintf("[SETUPEND]");
CLR_EP0_SETUP_END();
if(ep0_csr & EP0_OUT_PKT_READY)
{
FLUSH_EP0_FIFO(); //(???)
//I think this isn't needed because EP0 flush is done automatically.
CLR_EP0_OUT_PKT_RDY();
}
ep0State=EP0_STATE_INIT;
unmask_irq(INT_USBD);
return;
}
//I think that EP0_SENT_STALL will not be set to 1.
if(ep0_csr & EP0_SENT_STALL)
{
dbgprintf("[STALL]");
CLR_EP0_SENT_STALL();
if(ep0_csr & EP0_OUT_PKT_READY) CLR_EP0_OUT_PKT_RDY();
ep0State=EP0_STATE_INIT;
unmask_irq(INT_USBD);
return;
}
if((ep0_csr & EP0_OUT_PKT_READY) && (ep0State==EP0_STATE_INIT))
{
RdPktEp0((u8 *)&descSetup,EP0_PKT_SIZE);
// PrintEp0Pkt((u8 *)(&descSetup)); //DEBUG
switch(descSetup.bRequest)
{
case GET_DESCRIPTOR:
switch(descSetup.bValueH)
{
case DEVICE_TYPE:
dbgprintf("[GDD]");
CLR_EP0_OUT_PKT_RDY();
ep0State=EP0_STATE_GD_DEV_0;
break;
case CONFIGURATION_TYPE:
dbgprintf("[GDC]");
CLR_EP0_OUT_PKT_RDY();
if((descSetup.bLengthL+(descSetup.bLengthH<<8))>0x9)
//bLengthH should be used for bLength=0x209 at WIN2K.
ep0State=EP0_STATE_GD_CFG_0; //for WIN98,WIN2K
else
ep0State=EP0_STATE_GD_CFG_ONLY_0; //for WIN2K
break;
case STRING_TYPE:
dbgprintf("[GDS]");
CLR_EP0_OUT_PKT_RDY();
switch(descSetup.bValueL)
{
case 0:
ep0State=EP0_STATE_GD_STR_I0;
break;
case 1:
ep0State=EP0_STATE_GD_STR_I1;
break;
case 2:
ep0State=EP0_STATE_GD_STR_I2;
break;
default:
dbgprintf("[UE:STRI?]");
break;
}
ep0SubState=0;
break;
case INTERFACE_TYPE:
dbgprintf("[GDI]");
CLR_EP0_OUT_PKT_RDY();
ep0State=EP0_STATE_GD_IF_ONLY_0; //for WIN98
break;
case ENDPOINT_TYPE:
dbgprintf("[GDE]");
CLR_EP0_OUT_PKT_RDY();
switch(descSetup.bValueL&0xf)
{
case 0:
ep0State=EP0_STATE_GD_EP0_ONLY_0;
break;
case 1:
ep0State=EP0_STATE_GD_EP1_ONLY_0;
break;
default:
dbgprintf("[UE:GDE?]");
break;
}
break;
default:
dbgprintf("[UE:GD?]");
break;
}
break;
case SET_ADDRESS:
dbgprintf("[SA:%d]",descSetup.bValueL);
rFUNC_ADDR_REG=descSetup.bValueL | 0x80;
CLR_EP0_OUTPKTRDY_DATAEND(); //Because of no data control transfers.
ep0State=EP0_STATE_INIT;
break;
case SET_CONFIGURATION:
dbgprintf("[SC]");
CLR_EP0_OUTPKTRDY_DATAEND(); //Because of no data control transfers.
ep0State=EP0_STATE_INIT;
isUsbdSetConfiguration=1;
break;
default:
dbgprintf("[UE:SETUP=%x]",descSetup.bRequest);
CLR_EP0_OUTPKTRDY_DATAEND(); //Because of no data control transfers.
ep0State=EP0_STATE_INIT;
break;
}
}
switch(ep0State)
{
case EP0_STATE_INIT:
break;
//=== GET_DESCRIPTOR:DEVICE ===
case EP0_STATE_GD_DEV_0:
dbgprintf("[GDD0]");
WrPktEp0((u8 *)&descDev+0,8); //EP0_PKT_SIZE
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_DEV_1;
break;
case EP0_STATE_GD_DEV_1:
dbgprintf("[GDD1]");
WrPktEp0((u8 *)&descDev+0x8,8);
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_DEV_2;
break;
case EP0_STATE_GD_DEV_2:
dbgprintf("[GDD2]");
WrPktEp0((u8 *)&descDev+0x10,2); //8+8+2=0x12
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
break;
//=== GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 ===
//Windows98 gets these 4 descriptors all together by issuing only a request.
//Windows2000 gets each descriptor seperately.
case EP0_STATE_GD_CFG_0:
dbgprintf("[GDC0]");
WrPktEp0((u8 *)&descConf+0,8); //EP0_PKT_SIZE
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_CFG_1;
break;
case EP0_STATE_GD_CFG_1:
dbgprintf("[GDC1]");
WrPktEp0((u8 *)&descConf+8,1);
WrPktEp0((u8 *)&descIf+0,7);
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_CFG_2;
break;
case EP0_STATE_GD_CFG_2:
dbgprintf("[GDC2]");
WrPktEp0((u8 *)&descIf+7,2);
WrPktEp0((u8 *)&descEndpt0+0,6);
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_CFG_3;
break;
case EP0_STATE_GD_CFG_3:
dbgprintf("[GDC3]");
WrPktEp0((u8 *)&descEndpt0+6,1);
WrPktEp0((u8 *)&descEndpt1+0,7);
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_CFG_4;
break;
case EP0_STATE_GD_CFG_4:
dbgprintf("[GDC4]");
//zero length data packit
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
break;
//=== GET_DESCRIPTOR:CONFIGURATION ONLY===
case EP0_STATE_GD_CFG_ONLY_0:
dbgprintf("[GDCO0]");
WrPktEp0((u8 *)&descConf+0,8); //EP0_PKT_SIZE
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_CFG_ONLY_1;
break;
case EP0_STATE_GD_CFG_ONLY_1:
dbgprintf("[GDCO1]");
WrPktEp0((u8 *)&descConf+8,1);
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
break;
//=== GET_DESCRIPTOR:INTERFACE ONLY===
case EP0_STATE_GD_IF_ONLY_0:
dbgprintf("[GDI0]");
WrPktEp0((u8 *)&descIf+0,8);
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_IF_ONLY_1;
break;
case EP0_STATE_GD_IF_ONLY_1:
dbgprintf("[GDI1]");
WrPktEp0((u8 *)&descIf+8,1);
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
break;
//=== GET_DESCRIPTOR:ENDPOINT 0 ONLY===
case EP0_STATE_GD_EP0_ONLY_0:
dbgprintf("[GDE00]");
WrPktEp0((u8 *)&descEndpt0+0,7);
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
break;
//=== GET_DESCRIPTOR:ENDPOINT 1 ONLY===
case EP0_STATE_GD_EP1_ONLY_0:
dbgprintf("[GDE10]");
WrPktEp0((u8 *)&descEndpt1+0,7);
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
break;
//=== GET_DESCRIPTOR:STRING ===
case EP0_STATE_GD_STR_I0:
dbgprintf("[GDS0_0]");
WrPktEp0((u8 *)descStr0, 4 );
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
ep0SubState=0;
break;
case EP0_STATE_GD_STR_I1:
dbgprintf("[GDS1_%d]",ep0SubState);
if( (ep0SubState*EP0_PKT_SIZE+EP0_PKT_SIZE)<sizeof(descStr1) )
{
WrPktEp0((u8 *)descStr1+(ep0SubState*EP0_PKT_SIZE),EP0_PKT_SIZE);
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_STR_I1;
ep0SubState++;
}else{
WrPktEp0((u8 *)descStr1+(ep0SubState*EP0_PKT_SIZE),
sizeof(descStr1)-(ep0SubState*EP0_PKT_SIZE));
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
ep0SubState=0;
}
break;
case EP0_STATE_GD_STR_I2:
dbgprintf("[GDS2_%d]",ep0SubState);
if( (ep0SubState*EP0_PKT_SIZE+EP0_PKT_SIZE)<sizeof(descStr2) )
{
WrPktEp0((u8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),EP0_PKT_SIZE);
SET_EP0_IN_PKT_RDY();
ep0State=EP0_STATE_GD_STR_I2;
ep0SubState++;
}else{
dbgprintf("[E]");
WrPktEp0((u8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),
sizeof(descStr2)-(ep0SubState*EP0_PKT_SIZE));
SET_EP0_INPKTRDY_DATAEND();
ep0State=EP0_STATE_INIT;
ep0SubState=0;
}
break;
default:
dbgprintf("UE:G?D");
break;
}
unmask_irq(INT_USBD);
}
void WrPktEp1(u8 *buf, int num)
{
int i;
for(i=0;i<num;i++) rEP1_FIFO=buf[i];
}
void PrepareEp1Fifo(void)
{
int i;
u8 in_csr1;
rINDEX_REG = 1;
in_csr1 = rIN_CSR1_REG;
for(i=0;i<EP1_PKT_SIZE;i++) ep1Buf[i]=(u8)(transferIndex+i);
WrPktEp1(ep1Buf, EP1_PKT_SIZE);
SET_EP1_IN_PKT_READY();
}
void Ep1Handler(void)
{
u8 in_csr1;
int i;
rINDEX_REG=1;
in_csr1=rIN_CSR1_REG;
dbgprintf("<1:%x]",in_csr1);
//I think that EPI_SENT_STALL will not be set to 1.
if(in_csr1 & EPI_SENT_STALL)
{
dbgprintf("[STALL]");
CLR_EP1_SENT_STALL();
unmask_irq(INT_USBD);
return;
}
//IN_PKT_READY is cleared
//The data transfered was ep1Buf[] which was already configured
//PrintEpiPkt(ep1Buf,EP1_PKT_SIZE);
transferIndex++;
PrepareEp1Fifo();
//IN_PKT_READY is set
//This packit will be used for next IN packit.
unmask_irq(INT_USBD);
return;
}
void PrintEpoPkt(u8 *pt,int cnt)
{
int i;
dbgprintf("[BOUT:%d:",cnt);
for(i=0;i<cnt;i++) dbgprintf("%x,",pt[i]);
dbgprintf("]");
}
void RdPktEp3(u8 *buf,int num)
{
int i;
for(i=0;i<num;i++) buf[i]=(u8)rEP3_FIFO;
}
void RdPktEp3_CheckSum(u8 *buf,int num)
{
int i;
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