tempfile.tmp

board type like smdk2443 ARM920T processor

/*
 * Memory Setup stuff - taken from blob memsetup.S
 *
 * Copyright (C) 1999 2000 2001 Erik Mouw ([e-mail]) and
 *                     Jan-Derk Bakker ([e-mail])
 *
 * Modified for the Samsung SMDK2410 by
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <config.h>
#include <version.h>


/* some parameters for the board */

/*
 *
 * Taken from linux/arch/arm/boot/compressed/head-s3c2440.S
 *
 * Copyright (C) 2002 Samsung Electronics SW.LEE  <[e-mail]>
 *
 */
 /*** Mobile DRAM  Registers  */ 

#define BANKCON    	0x48000000
#define BANKCON1   	0x48000004
#define BANKCON2   	0x48000008
#define BANKCON3  	0x4800000c
#define REFRESH    	0x48000010

/** SMC: Static Memory Controller **/

#define SMBIDCYR0   	0x4F000000
#define SMBWSTRDR0  	0x4F000004
#define SMBWSTWRR0  	0x4F000008
#define SMBWSTOENR0 	0x4F00000C
#define SMBWSTWENR0 	0x4F000010
#define SMBCR0      	0x4F000014
#define SMBSR0      	0x4F000018
#define SMBWSTBRDR0 	0x4F00001C
#define SMBONETYPER     0x4F000100
#define SMCSR		0x4F000200
#define SMCCR		0x4F000204

/**** SDRAM 32 Bit Data Selcetion/Configuration Register **/ 
#define SDATACFG	0x560000E0

/**** BANKCFG register  : DRAM configure: Refer K4S56163PF - R(B)G/F Mobile SDRAM  Datasheet ***/

#define RASBW0 		 	2                       /*       RAS addr for Bank0, 10=13bit(A0 - A12)  : Page 1 */
#define RASBW1                  2                       /*       RAS addr for Bank1, 10=13bit(A0 - A12)  : Page 1 */
#define CASBW0                  1                       /*       CAS addr for Bank0, 01-9bit(A0 - A8)   : Page 1 */
#define CASBW1                  1                       /*       CAS addr for Bank0, 01-9bit(A0 - A8)   : Page 1 */
#define ADDRCFG0            	0                       /*       addre configure Bank 0    00={BA,RAS,CAS}, : Page 1  */
#define ADDRCFG1                0                       /*       addre configure BaNK 1    00={BA,RAS,CAS}, : Page 1  */
#define MEMCFG                  1                       /*       Ext.Mem 01=MSDR :   K4S56163PF is Mobile SDRAM */
#define BW                      0                       /*       Bus width 00=32bit  */

/*  BANKCON1 register : DRAM timing control */

#define BStop                   0                       /*      read burst stop control :Disabled: Page 6-7 of S3C2443 datashe                                                                   et */
#define WBUF                    1                       /*       write buffer control : Enabled : Recomended page 6-7 */
#define AP                      0                       /*       Disable auto precharge control for SDRAM*/
#define PWRDN                   0                       /*       Disable power down mode for SDRAM */

/*  BANKCON2 register : DRAM timing control (133MHz) */

#define tRAS                    6                       /*       7 clocks :50 ns :Row active time: Ref Page 7 of K4S56163PF **                                                                   /
#define tRC                     9                       /*       10 Clocks:72.5 ns: Row cycle time : Ref Page 7 of K4S56163PF                                                                   **/
#define CL                      3                       /*       CAS latency control */
#definet RCD                    2                       /*       3 clocks: RAS to CAS delay : Ref Page 7 of K4S56163PF */
#define tRP                     2                       /*       3 clocks: Row pre-charge time : Ref Page 7 of K4S56163PF */


/*  BANKCON3 register : MRS/EMRS register */

#define BA_EMRS                 2                       /*       10 : BA  EMRS:  Ref Page 10 of K4S56163PF */
#define DS                      0                       /*       Full Driver strength */
#define PASR                    0                       /*       Full Array Refresh PASR */ 
#define BA_MRS                  0                       /*       BA : Normal MRS  */
#define TM                      0                       /*       Reserved to 0  */
#define CL_MRS                  3                       /*       CAS Latency */

/*  REFRESH register : refresh register */

#define REFCYC                  8512000                    /*      Refresh Period = 64 ms: :REFCYC = 64 x 10-3 x 133 x 10+6 =                                                                    8512 Ref Page 5 of K4S56163PF  */ 


/*    SMC Configuration : nRCS0  for Ethernet Controller RTL8303   */

#define IDCY0                   ***                     /*      **** To be found:   Idle or turnaround cycles IDCY*HCLK */ 
<<<<<<< .mine
#define WSTRD0                  2                       /*      3 clocks: Read wait state = tacc = 3 * SMCLK: ref RTL8303 Page                                                                74: t3 is 18 ns for Reg Read For NIC Buffer Select tacc = 28 n                                                                  s : select WSTRD = 4 clocks */
=======
#define WSTRD0                  2                      /*       3 clocks: Read wait state = tacc = 3 * SMCLK: ref RTL8303 Page 74: t3 is 18 ns for Reg Read  								        For NIC Buffer Select tacc = 28 ns : select WSTRD = 4 clocks */
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#define WSTWR0                  2                      /*       3 clocks: write wait state */
#define WSTOEN0                 0                       /*      No Delay from CS <--> ROE(RD) output enable assertion delay fr                                                                om CS: Page 74 of RTL8303  */
#define WSTWEN0                 0                       /*      No Delay from CS <--> RWE(WR) write enable assertion delay : P                                                                age 74 of RTL8303   */
#define BlWriteEn               1                       /*	bit21-SMBAA signal control:0-1at all times, 1 active for sync                                                                   */
#define AddrValidWriteEn        0                       /*	bit20-SMADDRVALD during write:0-always high,1-active for write                                                                */
#define BurstLenWrite           0                       /*	4 transfer burst:  bit1819-burst transfer length:0-4,1-8,3-con                                                                tinu(sync only) */
#define SyncWriteDev            0                       /*	RTL8303 is in asynchronous SRAM access: bit17-0:async, 1:sync                                                                 Reserved */
#define BMWrite                 0                       /*	Does not support Burst Mode Write: bit16-burt mode write : 0-n                                                                on-burst, 1-burst */
#define WrapRead                0                       /*	bit14-0-disable, 1 enable */
#define BlReadEn                1                       /*	bit13-SMBAA signal :0-1 at all time, 1-active for sync read: s                                                                hould be high  */
#define AddrValidReadEn         0                       /*	NO Synchronous access : bit12-SMADDRVALID signal is used when                                                                 access synchronous device in 
                                                                Asynchromous Mode: 0-always HIGH,  */
#define BurstLenRead            0                       /*	Support 4 Burst Reads : bit1011-burst transfer length:0-4,1-8,                                                                2-16,3-cont(sync only)
                                                                SMC supports only 4 or 8 burst reads */
#define SyncReadDev             0                       /*	RTL8303 is in asynchronous SRAM access: bit9-sync access :0-as                                                                ync, 1-sync */
#define BMRead                  1                       /*	Burst Mode Read Enabled: bit8-burst mode read and async page m                                                                ode */
#define SMBLSPOL                1                       /*	Active High: RBE[1:0] <---> BA[1:0]: bit6-polarity of signal n                                                                SMBLS */
#define MW                      1                       /*	16 bit Data Access : bit45-memory width : 00-8bit,01-16bit, **                                                           */
#define WP                      0                       /*	No Write Protect : bit3-write protect */
#define WaitEn                  0                       /*	Disabled :bit2-external wait signal enable */
#define WaitPol                 0                       /*	Not used: 0 by default: bit1-polarity of the external wait inp                                                                ut for actiation */
#define RBLE                    1                       /*	bit0- byte lane enable not Used for 16 bit
                                                         *      Data bcz s3c2443 is having separate RWE : Ref Page 5-17 of s3c                                                                 2443  */
#define SMBCR0_0                ((BMRead<<8)+(SMBLSPOL<<6)+(MW<<4)+(WP<<3)+(WaitEn<<2)+(WaitPol<<1)+RBLE)
#define SMBCR0_1                ((WrapRead<<14)+(BlReadEn<<13)+(AddrValidReadEn<<12)+(BurstLenRead<<10)+(SyncReadDev<<9))
#define SMBCR0_2                ((BlWriteEn<<21)+(AddrValidWriteEn<<20)+(BurstLenWrite<<18)+(SyncWriteDev<<17)+(BMWrite<<16))
#define WaitTourErr0            0                       /*	external wait timeout error flag */
#define WSTBRD0                 2                       /*	WSTBRD = 3 clk = 22 ns = t5 : burst read wait state  Ref t4 &                                                              t5 from Page 75 of 8303  */
#define MemClkRatio             0                       /*	SMCLK = HCLK = 133 Mhz: SMMEMCLK :0-HCLK,1-HCLK/2,2-HCLK/3 */ 
#define SMClockEn               1                       /*	SMCLK enable 1-always running */


/**************************************/

_TEXT_BASE:
	.word	TEXT_BASE

.globl memsetup
memsetup:

        /*    Memory Controller Condiguration SMC  set nRCS0 for Ethernet Controller RTL8303       */
         ldr             r0,=SMBIDCYR0
         ldr             r1,=IDCY0
         str             r1,[r0]

         ldr             r0,=SMBWSTRDR0
         ldr             r1,=WSTRD0
         str             r1,[r0]

         ldr             r0,=SMBWSTWRR0
         ldr             r1,=WSTWR0
         str             r1,[r0]

         ldr             r0,=SMBWSTOENR0
         ldr             r1,=WSTOEN0
         str             r1,[r0]

         ldr             r0,=SMBWSTWENR0
         ldr             r1,=WSTWEN0
         str             r1,[r0]

         ldr             r0,=SMBCR0
         ldr             r1,=(SMBCR0_2+SMBCR0_1+SMBCR0_0)
         str             r1,[r0]   

	 ldr             r0,=SMBWSTBRDR0
         ldr             r1,=WSTBRD0
         str             r1,[r0]

         ldr             r0,=SMCCR
         ldr             r1,=((MemClkRatio<<1)+(SMClockEn<<0))
         str             r1,[r0]

 /* Set SDATACFG Config Register to control 32bit SDRAM width. */
         ldr             r0,=SDATACFG
         ldr             r1,=0xaaaaaaaa  ; set Sdata[31:16]
         str             r1, [r0]


/* SDRAM memory control configuration */
/* make r0 relative the current location so that it */
/* reads SMRDATA out of FLASH rather than memory ! */
	 ldr     r0, =SMRDATA
	 ldr	r1, _TEXT_BASE
	 sub	r0, r0, r1

 /*
  *       Setting the Configuration BANKCFG . This is for MRS and EMRS command to DRAM.
  *	 Program the Control Register  BANKCON1  and BANKCON3  to their normal operation values 
  */
        ldr     r1, =BANKCFG
	add     r2, r0, #4*4
0:
	ldr     r3, [r0], #4
	str     r3, [r1], #4
	cmp     r2, r0
	bne     0b
 
 	ldr     r2,=BANKCON1
        ldr     r1,[r2]
        bic     r1,r1,#(0x3<<0)
        orr     r1,r1,#(0x1<<0)                /*       4th        Issue a PALL command */
        str     r1,[r2]

        ldr     r4,=REFRESH                    /*       5fh : refresh cycle every 255-clock cycles */
        ldr     r0,=0xff
        str     r0,[r4]

  	mov     r0, #0x100                     /*       6th : wait 2 auto - clk */
0       subs    r0, r0,#1;
        bne     %B0

        bic             r1,r1,#(0x3<<0)        /*       7th     :       Issue a MRS command */
        orr             r1,r1,#(0x2<<0)
        str             r1,[r2]

        ldr             r4,=REFRESH            /*       8fh : refresh  normal */
        ldr             r0,=REFCYC
        str             r0,[r4]

        orr             r1,r1,#(0x3<<0)        /*       9th     :       Issue a EMRS command */
        str             r1,[r2]
        bic             r1,r1,#(0x3<<0)        /*       10th    :       Issue a Normal mode */
        str             r1,[r2]

	/* everything is fine now */
	mov	pc, lr

	.ltorg
/* the literal pools origin */

SMRDATA:
    .word ((RASBW0<<17)+(RASBW1<<14)+(CASBW0<<11)+(CASBW1<<8)+(ADDRCFG0<<6)+(ADDRCFG1<<4)+(MEMCFG<<2)+(BW<<0))
    .word ((BStop<<7)+(WBUF<<6)+(AP<<5)+(PWRDN<<4))
    .word ((tRAS<<20)+(tRC<<16)+(CL<<4)+(tRCD<<2)+(tRP<<0))
    .word ((BA_EMRS<<30)+(DS<<21)+(PASR<<16)+(BA_MRS<<14)+(TM<<7)+(CL_MRS<<4))