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📄 tempfile.2.tmp

📁 board type like smdk2443 ARM920T processor
💻 TMP
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/* * (C) Copyright 2006 OpenMoko, Inc. * Author: Harald Welte <laforge@openmoko.org> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h><<<<<<< .mine//#include <s3c2440.h>#include <s3c2443.h>=======#include <s3c2443.h>>>>>>>> .r159DECLARE_GLOBAL_DATA_PTR;#define FCLK_SPEED 1#if FCLK_SPEED==0		#define M_MDIV	0xC3#define M_PDIV	0x4#define M_SDIV	0x1#elif FCLK_SPEED==1		/* Fout = 1068 MHz */#define M_MDIV	0x51#define M_PDIV	0x2#define M_SDIV	0x0#endif#define USB_CLOCK 1#if USB_CLOCK==0#define U_M_MDIV	0x28#define U_M_PDIV	0x1#define U_M_SDIV	0x1#elif USB_CLOCK==1            /* Fout = 96 MHz */        #define E_M_MDIV	0x28                #define E_M_PDIV	0x1#define E_M_SDIV	0x1#endifstatic inline void delay (unsigned long loops){	__asm__ volatile ("1:\n"	  "subs %0, %1, #1\n"	  "bne 1b":"=r" (loops):"0" (loops));}/* * Miscellaneous platform dependent initialisations */int board_init (void){	S3C2443_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();	S3C2443_GPIO * const gpio = S3C24X0_GetBase_GPIO();	/* to reduce PLL lock time, adjust the LOCKTIME register */	clk_power->LOCKCON0 = 0xFFFFFF;	clk_power->LOCKCON0 = 0xFFFFFF;	/* configure MPLL */	clk_power->MPLLCON = ((M_MDIV << 16) + (M_PDIV << 8) + M_SDIV);	/* some delay between MPLL and EPLL */	delay (4000);	/* configure EPLL */	clk_power->UPLLCON = ((E_M_MDIV << 16) + (E_M_PDIV << 8) + E_M_SDIV);	/* some delay between MPLL and EPLL */	delay (8000);	/* set up the I/O ports */	gpio->GPACDL = 0x0000AAAA;    /*  RADDR0 & RADDR16 <--> RADDR22  */        gpio->GPACDH = 0x0000AAAA;   /* select  nRSTOUT = low #Ethernet Controller(RTL8303) #RESET is active low: Ref Page 17 ***/        /** To be Done Later  	gpio->GPBCON = 0x00044555;	gpio->GPBUP = 0x000007FF;	gpio->GPCCON = 0xAAAAAAAA;	gpio->GPCUP = 0x0000FFFF;	gpio->GPDCON = 0xAAAAAAAA;	gpio->GPDUP = 0x0000FFFF;	gpio->GPECON = 0xAAAAAAAA;	gpio->GPEUP = 0x0000FFFF;	gpio->GPFCON = 0x000055AA;	gpio->GPFUP = 0x000000FF;	gpio->GPGCON = 0xFD95FFBA;	gpio->GPGUP = 0x0000FFFF;#ifdef CONFIG_SERIAL3	gpio->GPHCON = 0x002AAAAA;#else	gpio->GPHCON = 0x002AFAAA;#endif	gpio->GPHUP = 0x000007FF;       */#if 0	/* USB Device Part */	/*GPGCON is reset for USB Device */	gpio->GPGCON = (gpio->GPGCON & ~(3 << 24)) | (1 << 24); /* Output Mode */	gpio->GPGUP = gpio->GPGUP | ( 1 << 12);			/* Pull up disable */	gpio->GPGDAT |= ( 1 << 12) ;	gpio->GPGDAT &= ~( 1 << 12) ;	udelay(20000);	gpio->GPGDAT |= ( 1 << 12) ;#endif	/* arch number of SMDK2443-Board */	gd->bd->bi_arch_number = MACH_TYPE_S3C2443;	/* adress of boot parameters */	gd->bd->bi_boot_params = 0x30000100;	icache_enable();	dcache_enable();	return 0;}int dram_init (void){	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;        gd->bd->bi_dram[1].start = PHYS_SDRAM_2;	gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;	return 0;}/* The sum of all part_size[]s must equal to the NAND size, i.e., 0x8000000.   "initrd" is sized such that it can hold two uncompressed 16 bit 640*480   images: 640*480*2*2 = 1228800 < 1245184. */unsigned int dynpart_size[] = {    CFG_UBOOT_SIZE, 0x20000, 0x200000, 0xa0000, 0x7d5c000-CFG_UBOOT_SIZE, 0 };char *dynpart_names[] = {    "u-boot", "u-boot_env", "kernel", "splash", "rootfs", NULL };

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