start.s.svn-base

u-boot for S3c2443 processor

/*
 *  armboot - Startup Code for ARM920 CPU-core
 *
 *  Copyright (c) 2001	Marius Gr�ger <[e-mail]>
 *  Copyright (c) 2002	Alex Z�pke <[e-mail]>
 *  Copyright (c) 2002	Gary Jennejohn <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <config.h>
#include <version.h>

#if defined(CONFIG_S3C2440)
 #include <s3c2440.h>
#elif defined(CONFIG_S3C2443)
 #include <s3c2443.h>
#endif

/*************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************/

.globl _start
_start:	b       reset
	ldr	pc, _undefined_instruction
	ldr	pc, _software_interrupt
	ldr	pc, _prefetch_abort
	ldr	pc, _data_abort
	ldr	pc, _not_used
	ldr	pc, _irq
	ldr	pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq

	.balignl 16,0xdeadbeef


/*************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * relocate armboot to ram
 * setup stack
 * jump to second stage
 *
 **************************************************************************/

_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/* These are defined in the board-specific linker script. */
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif


/****************************************************
 * the actual reset code 
 ****************************************************/

reset:
	/* set the cpu to SVC32 mode */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0


#if defined(CONFIG_S3C2400)
#define pWTCON		0x15300000
#define INTMSK		0x14400008
#define CLKDIVN		0x14800014

#elif defined(CONFIG_S3C2410)
#define pWTCON		0x53000000
#define INTMSK		0x4A000008
#define INTSUBMSK	0x4A00001C
#define CLKDIVN		0x4C000014

#elif defined(CONFIG_S3C2440)
#define INTMSK      0x4A000008
#define INTSUBMSK   0x4A00001C
#define pWTCON      0x53000000
#define INTMSK      0x4A000008
#define INTSUBMSK   0x4A00001C
#define LOCKTIME    0x4C000000
#define CLKDIVN     0x4C000014
#define MPLLCON     0x4C000004
#define UPLLCON     0x4C000008

#elif defined(CONFIG_S3C2443)
#define pWTCON      0x53000000
#define INTMSK      0x4A000008
#define INTSUBMSK   0x4A00001C
# define INTSUBMSK_val 0x1fffffff
/*
	Fin = 12MHz,
        
	MPLLout = (2m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV, s=SDIV, Fin=10~30MHz
        MDIV=81 PDIV=2 SDIV=0
        MPLLout=1068Mhz 
  
        EPLLout = (m x Fin)/(p x 2**s), m=MDIV+8, p=PDIV+2, s=SDIV, Fin=10~100MHz;       
        MDIV=40 PDIV=1 SDIV=1
        EPLLout = 96Mhz
       
*/

# define EPLLCON_val   ((40 << 16) | (1 << 8) | (1))           /* 96 MHz */
# define MPLLCON_val   ((81 << 16) | (2 << 8) | (0))           /* 1068 MHz */

/*
     MPLL CLock = 1066Mhz 

     ARMDIV  = 8           : ARMCLK  		= MPLL/2  		//  533 Mhz
     PREDIV  = 1   	   : PREDIV_CLK      	= ARMCLK/2      	//  266 Mhz
     HCLKDIV = 1    	   : HCLK		=PREDIV_CLK/2		//  133 Mhz
     PCLKDIV = 1	   : PCLK    		= HCLK/2		//   66 Mhz
     HALFHCLK =1	   : SSMCCLK    	= HCLK/2		//  66 Mhz
     
            : 
*/
# define CLKDIV0_val   ((8 << 9) | (1 << 4) | (1 << 3) | (1 << 2) | (1 << 0) 
#endif

	/* turn off the watchdog */
	ldr     r0, =pWTCON
	mov     r1, #0x0
	str     r1, [r0]

	/* mask all IRQs by setting all bits in the INTMR - default */
	mov	r1, #0xffffffff
	ldr	r0, =INTMSK
	str	r1, [r0]
#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
	ldr	r1, =0x3ff
	ldr	r0, =INTSUBMSK
	str	r1, [r0]
#elif defined(CONFIG_S3C2443)
        ldr     r1, =INTSUBMSK_val
        ldr     r0, =INTSUBMSK
        str     r1, [r0]
#endif

#if CONFIG_S3C2410
	/* FCLK:HCLK:PCLK = 1:2:4 */
	/* default FCLK is 120 MHz ! */
	ldr	r0, =CLKDIVN
	mov	r1, #3
	str	r1, [r0]
#elif CONFIG_S3C2440
    ldr r0, =LOCKTIME
    ldr r1, =0xffffffff
    str r1, [r0]

    /* FCLK:HCLK:PCLK = 1:3:6 */
    ldr r0, =CLKDIVN
@	ldr r1, =7		@ 1:3:6
	ldr r1, =5		@ 1:4:8
    str r1, [r0]

    /* MMU SetAsyncBusMode */
    mrc p15, 0, r0, c1, c0, 0
    orr r0,r0,#0xc0000000
    mcr p15,0,r0,c1,c0,0

    /* UPLL configuration */
    ldr r0, =UPLLCON
    ldr r1, =0x0003c042 /* MDIV=60,PDIV=4,SDIV=1 */
    str r1, [r0]

    nop
    nop
    nop
    nop
    nop
    nop
    nop

    /* MPLL configuration */
    ldr r0, =MPLLCON
    ldr r1, =0x6e031 /* MDIV=110,PDIV=3,SDIV=1 */
    str r1, [r0]
#elif defined(CONFIG_S3C2443)

	ldr	r0, =CLKDIV0
	ldr	r1, =CLKDIV0_val
	str	r1, [r0]

       	/* MMU SetAsyncBusMode */
    	mrc p15, 0, r0, c1, c0, 0
    	orr r0,r0,#0xc0000000
    	mcr p15,0,r0,c1,c0,0 

	/* set safe (way too long) locktime for both PLLs */
	ldr	r0, =LOCKCON0
	mov	r1, #0xffffff
	str	r1, [r0]
	ldr	r0, =LOCKCON1
	str	r1, [r0]

	/* configure MPLL */
	ldr	r0, =MPLLCON
	ldr	r1, =MPLLCON_val
	str	r1, [r0]

	/* select MPLL clock out for SYSCLK: Use MPLL clock O/P as SYSCLK   */
	ldr	r0, =CLKSRC
	ldr	r1, [r0]
	orr	r1, r1, #0x10     
	str	r1, [r0]

	/* configure EPLL */
	ldr	r0, =EPLLCON
	ldr	r1, =EPLLCON_val
	str	r1, [r0]

#endif

	/* we do sys-critical inits only at reboot,
	 * not when booting from ram! */

#if CONFIG_INIT_CRITICAL
	bl	cpu_init_crit
#endif

#if CONFIG_NAND_BOOT
	bl	copy_from_nand
#endif

relocate:				/* relocate U-Boot to RAM	    */
	adr	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE	/* test if we run from flash or RAM */
	cmp     r0, r1      /* don't reloc during debug         */
	beq     stack_setup

	ldr	r2, _armboot_start
	ldr	r3, _bss_start
	sub	r2, r3, r2		/* r2 <- size of armboot            */
	add	r2, r0, r2		/* r2 <- source end address         */

copy_loop:
	ldmia	r0!, {r3-r10}	/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}	/* copy to   target address [r1]    */
	cmp	r0, r2				/* until source end addreee [r2]    */
	ble	copy_loop

	/* Set up the stack	*/
stack_setup:
	ldr	r0, _TEXT_BASE				/* upper 128 KiB: relocated uboot   */
	sub	r0, r0, #CFG_MALLOC_LEN		/* malloc area                      */
	sub	r0, r0, #CFG_GBL_DATA_SIZE 	/* bdinfo                        */
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */

clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
	add	r0, r0, #4			/* start at first byte of bss       */
	ldr	r1, _bss_end		/* stop here                        */
	mov 	r2, #0x00000000	/* clear                            */

clbss_l:str	r2, [r0]		/* clear loop...                    */
	add	r0, r0, #4
	cmp	r0, r1
	bne	clbss_l

	ldr	pc, _start_armboot

_start_armboot:	.word start_armboot


/*************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 **************************************************************************/


cpu_init_crit:
	/* flush v4 I/D caches */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/* disable MMU stuff and caches */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	@ clear bits 13, 9:8 (--V- --RS)
	bic	r0, r0, #0x00000087	@ clear bits 7, 2:0 (B--- -CAM)
	orr	r0, r0, #0x00000002	@ set bit 2 (A) Align
	orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
	mcr	p15, 0, r0, c1, c0, 0


	/* before relocating, we have to setup RAM timing
	 * because memory timing is board-dependend, you will
	 * find a memsetup.S in your board directory. */
	mov	ip, lr
	bl	memsetup
	mov	lr, ip

	mov	pc, lr


/*************************************************************************
 *
 * Interrupt handling
 *
 **************************************************************************/

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/* use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling */

	.macro	bad_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	ldr	r2, _armboot_start
	sub	r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
	sub	r2, r2, #(CFG_GBL_DATA_SIZE+8)  @ set base 2 words into abort stack
	ldmia	r2, {r2 - r3}			@ get pc, cpsr
	add	r0, sp, #S_FRAME_SIZE		@ restore sp_SVC

	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}			@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	add     r8, sp, #S_PC
	stmdb   r8, {sp, lr}^                   @ Calling SP, LR
	str     lr, [r8, #0]                    @ Save calling PC
	mrs     r6, spsr
	str     r6, [r8, #4]                    @ Save CPSR
	str     r0, [r8, #8]                    @ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4			@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, _armboot_start		@ setup our mode stack
	sub	r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
	sub	r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack

	str	lr, [r13]			@ save caller lr / spsr
	mrs	lr, spsr
	str     lr, [r13, #4]

	mov	r13, #MODE_SVC			@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13
	mov	lr, pc
	movs	pc, lr
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm

/* exception handlers */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl 	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl 	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl 	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl 	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl 	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl 	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl 	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl 	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl 	do_fiq

#endif

	.align	5
.globl reset_cpu
reset_cpu:
#ifdef CONFIG_S3C2400
	bl	disable_interrupts
# ifdef CONFIG_TRAB
	bl	disable_vfd
# endif
	ldr	r1, _rWTCON
	ldr	r2, _rWTCNT
	/* Disable watchdog */
	mov	r3, #0x0000
	str	r3, [r1]
	/* Initialize watchdog timer count register */
	mov	r3, #0x0001
	str	r3, [r2]
	/* Enable watchdog timer; assert reset at timer timeout */
	mov	r3, #0x0021
	str	r3, [r1]
_loop_forever:
	b	_loop_forever
_rWTCON:
	.word	0x15300000
_rWTCNT:
	.word	0x15300008
#else /* ! CONFIG_S3C2400 */
	mov     ip, #0
	mcr     p15, 0, ip, c7, c7, 0           @ invalidate cache
	mcr     p15, 0, ip, c8, c7, 0           @ flush TLB (v4)
	mrc     p15, 0, ip, c1, c0, 0           @ get ctrl register
	bic     ip, ip, #0x000f                 @ ............wcam
	bic     ip, ip, #0x2100                 @ ..v....s........
	mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
	mov     pc, r0
#endif /* CONFIG_S3C2400 */


#if CONFIG_NAND_BOOT
copy_from_nand:
	mov r10, lr
	ldr sp, =0x33fffffc
	mov fp, #0
	
	bl copy_uboot_func
	ldr r0, _TEXT_BASE
	add pc, r10, r0

#endif