tempfile.2.tmp

u-boot for S3c2443 processor

/*
 * (C) Copyright 2001-2002
 * Wolfgang Denk, DENX Software Engineering, [e-mail].
 *
 * (C) Copyright 2002
 * David Mueller, ELSOFT AG, [e-mail]
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* This code should work for both the S3C2400 and the S3C2410
 * as they seem to have the same PLL and clock machinery inside.
 * The different address mapping is handled by the s3c24xx.h files below.
 */

#include <common.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#elif defined(CONFIG_S3C2440)
#include <s3c2440.h>
<<<<<<< .mine
#elif defined(CONFIG_S3C2443) //added by maddy20012009
#include <s3c2443.h>  
=======
#elif defined(CONFIG_S3C2443)
#include <s3c2443.h>
>>>>>>> .r159
#endif


#define MPLL 0
#if defined(CONFIG_S3C2440)
#define UPLL 1
#elif defined(CONFIG_S3C2443)
#define EPLL 1

/* ------------------------------------------------------------------------- */
/* NOTE: This describes the proper use of this file.
 *
 * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
 *
 * get_FCLK(), get_HCLK(), get_PCLK() and get_UCLK() return the clock of
 * the specified bus in HZ.
 */
/* ------------------------------------------------------------------------- */

static ulong get_PLLCLK(int pllreg)
{
    #if defined(CONFIG_S3C2443)
	S3C2443_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
    #else
	S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
    #endif 
    ulong r, m, p, s;

    if (pllreg == MPLL)		r = clk_power->MPLLCON;
    #if defined(CONFIG_S3C2443)
    else if (pllreg == EPLL)	r = clk_power->EPLLCON;
    #else
    else if (pllreg == UPLL)	r = clk_power->UPLLCON;
    #endif
    else			hang();
   
    #if defined(CONFIG_S3C2443)
    m = ((r & 0xFF000) >> 16) + 8;
    if (pllreg == MPLL)
    p = ((r & 0x003F0) >> 8);
    else
    p = ((r & 0x003F0) >> 8) + 2; 
    s = r & 0x3;
    #else
    m = ((r & 0xFF000) >> 12) + 8;
    p = ((r & 0x003F0) >> 4) + 2;
    s = r & 0x3;
    #endif 

    #if defined(CONFIG_S3C2410)
    return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
    #elif defined(CONFIG_S3C2440)
	if(pllreg == MPLL)
		return ((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s));
	else if(pllreg == UPLL)
		return ((CONFIG_SYS_CLK_FREQ * m) / (p << s));
    #elif defined(CONFIG_S3C2443)
	if(pllreg == MPLL)
		return ((CONFIG_SYS_CLK_FREQ * m * 2) / (p << s));
	else if(pllreg == EPLL)
		return ((CONFIG_SYS_CLK_FREQ * m) / (p << s));
    #endif
    
}

/* return FCLK frequency */
ulong get_FCLK(void)
{
    return(get_PLLCLK(MPLL));
}

/* return PREDIV_CLK frequency */
ulong get_PDIV_CLK()
{
	S3C2443_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
	
        switch(clk_power->CLKDIVN & 0x30){
		case 0:
			return get_FCLK()/1;
		case 16:
			return get_FCLK()/2;
                case 32:
			return get_FCLK()/3;
		case 48:
			return get_FCLK()/4;
         }
 } 

/* return HCLK frequency */
ulong get_HCLK(void)
{
	#if defined(CONFIG_S3C2443)
	    S3C2443_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
	#else
	    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
	#endif

	#if defined(CONFIG_S3C2410)
	    return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
	#elif defined(CONFIG_S3C2440)
	    switch(clk_power->CLKDIVN & 0x6){
		case 0:
			return get_FCLK();
		case 2:
			return get_FCLK()/2;
		case 4:
			return get_FCLK()/4;
		case 6:
			return get_FCLK()/3;
		default:
			return get_FCLK()/4;
	}
	#elif defined(CONFIG_S3C2443)
	    switch(clk_power->CLKDIV0 & 0x1){
		case 0:
			return get_PDIV_CLK();
		case 1:
			return get_PDIV_CLK()/2;
	    }
	#endif
  }

/* return PCLK frequency */
ulong get_PCLK(void)
 {
	#if defined(CONFIG_S3C2443)
	    S3C2443_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
	#else
	    S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
	#endif
        #if defined(CONFIG_S3C2443)
            switch(clk_power->CLKDIV0 & 0x4){
	#else
	    switch(clk_power->CLKDIVN & 0x1){
        #endif
		case 0:
			return get_HCLK()/1;
		case 1:
                case 4:
			return get_HCLK()/2;
	}
}

/* return UCLK frequency */
ulong get_UCLK(void)
{
    return(get_PLLCLK(UPLL));
}

/* return ECLK frequency */
ulong get_ECLK(void)
{
    return(get_PLLCLK(EPLL));
}