sc520_asm.s.svn-base

u-boot for S3c2443 processor

	movl    $ROW14_ADR, %esi         /* set address to max row (14) wrap addr */
	movl    $ROW14_DATA, %eax        /* pattern for max supported rows(14) */
	movl    %eax, (%esi)             /* write max row pattern at max row adr */
	movl    (%esi), %ebx             /* optional read */
	cmpl    %ebx,%eax                /* to verify write */
	jnz     bad_ram                  /* this ram is bad */
 /*
  * write row 13 wrap adr
  */
	movl    $ROW13_ADR, %esi         /* set address to 13 row wrap address */
	movl    $ROW13_DATA, %eax        /* pattern for 13 row wrap */
	movl    %eax, (%esi)             /* write 13 row pattern @ 13 row wrap adr */
	movl    (%esi), %ebx             /* optional read */
	cmpl    %ebx,%eax                /* to verify write */
	jnz     bad_ram                  /* this ram is bad */
 /*
  * write row 12 wrap adr
  */
	movl    $ROW12_ADR, %esi         /* set address to 12 row wrap address */
	movl    $ROW12_DATA, %eax        /* pattern for 12 row wrap */
	movl    %eax, (%esi)             /* write 12 row pattern @ 12 row wrap adr */
	movl    (%esi), %ebx             /* optional read */
	cmpl    %ebx,%eax                /* to verify write */
	jnz     bad_ram                  /* this ram is bad */
 /*
  * write row 11 wrap adr
  */
	movl    $ROW11_ADR, %edi         /* set address to 11 row wrap address */
	movl    $ROW11_DATA, %eax        /* pattern for 11 row wrap */
	movl    %eax, (%edi)             /* write 11 row pattern @ 11 row wrap adr */
	movl    (%edi), %ebx             /* optional read */
	cmpl    %ebx,%eax                /* to verify write */
	jnz     bad_ram                  /* this ram is bad */
 /*
  * write row 10 wrap adr --- this write is really to determine number of banks
  */
	movl    $ROW10_ADR, %edi         /* set address to 10 row wrap address */
	movl    $ROW10_DATA, %eax        /* pattern for 10 row wrap (AA) */
	movl    %eax, (%edi)             /* write 10 row pattern @ 10 row wrap adr */
	movl    (%edi), %ebx             /* optional read */
	cmpl    %ebx,%eax                /* to verify write */
	jnz     bad_ram                  /* this ram is bad */
 /*
  * read data @ row 12 wrap adr to determine  * banks,
  * and read data @ row 14 wrap adr to determine  * rows.
  * if data @ row 12 wrap adr is not AA, 11 or 12 we have bad RAM.
  * if data @ row 12 wrap == AA, we only have 2 banks, NOT 4
  * if data @ row 12 wrap == 11 or 12, we have 4 banks,
  */
	xorw    %di,%di                  /* value for 2 banks in DI */
	movl    (%esi), %ebx             /* read from 12 row wrap to check banks
					  * (esi is setup from the write to row 12 wrap) */
	cmpl    %ebx,%eax                /* check for AA pattern  (eax holds the aa pattern) */
	jz      only2                    /* if pattern == AA, we only have 2 banks */

	/* 4 banks */

	movw    $8,%di                   /* value for 4 banks in DI (BNK_CNT bit) */
	cmpl    $ROW11_DATA, %ebx        /* only other legitimate values are 11 */
	jz      only2
	cmpl    $ROW12_DATA, %ebx        /* and 12 */
	jnz     bad_ram                  /* its bad if not 11 or 12! */

	/* fall through */
only2:
 /*
  * validate row mask
  */
	movl    $ROW14_ADR, %esi         /* set address back to max row wrap addr */
	movl    (%esi), %eax             /* read actual number of rows @ row14 adr */

	cmpl    $ROW11_DATA, %eax        /* row must be greater than 11 pattern */
	jb      bad_ram

	cmpl    $ROW14_DATA, %eax        /* and row must be less than 14 pattern */
	ja      bad_ram

	cmpb    %ah,%al                  /* verify all 4 bytes of dword same */
	jnz     bad_ram
	movl    %eax,%ebx
	shrl    $16,%ebx
	cmpw    %bx,%ax
	jnz     bad_ram
 /*
  * read col 11 wrap adr for real column data value
  */
	movl    $COL11_ADR, %esi         /* set address to max col (11) wrap addr */
	movl    (%esi), %eax             /* read real col number at max col adr */
 /*
  * validate column data
  */
	cmpl    $COL08_DATA, %eax        /* col must be greater than 8 pattern */
	jb      bad_ram

	cmpl    $COL11_DATA, %eax        /* and row must be less than 11 pattern */
	ja      bad_ram

	subl    $COL08_DATA, %eax        /* normalize column data to zero */
	jc      bad_ram
	cmpb    %ah,%al                  /* verify all 4 bytes of dword equal */
	jnz     bad_ram
	movl    %eax,%edx
	shrl    $16,%edx
	cmpw    %dx,%ax
	jnz     bad_ram
 /*
  * merge bank and col data together
  */
	addw    %di,%dx                  /* merge of bank and col info in dl */
 /*
  * fix ending addr mask based upon col info
  */
	movb    $3,%al
	subb    %dh,%al                  /* dh contains the overflow from the bank/col merge  */
	movb    %bl,%dh                  /* bl contains the row mask (aa, 07, 0f, 1f or 3f) */
	xchgw   %cx,%ax                  /* cx = ax = 3 or 2 depending on 2 or 4 bank device */
	shrb    %cl,%dh	                 /*  */
	incb    %dh                      /* ending addr is 1 greater than real end */
	xchgw   %cx,%ax                  /* cx is bank number again */
 /*
  * issue all banks precharge
  */
bad_reint:
	movl    $DRCCTL, %esi            /* setup DRAM control register with */
	movb    $0x2,%al                 /* All banks precharge */
	movb     %al, (%esi)
	movl    $CACHELINESZ, %esi       /* address to init read buffer */
	movw     %ax, (%esi)

 /*
  * update ENDING ADDRESS REGISTER
  */
	movl    $DRCBENDADR, %edi        /* DRAM ending address register */
	movl    %ecx,%ebx
	addl	%ebx, %edi
	movb    %dh, (%edi)
 /*
  * update CONFIG REGISTER
  */
	xorb    %dh,%dh
	movw    $0x00f,%bx
	movw    %cx,%ax
	shlw    $2,%ax
	xchgw   %cx,%ax
	shlw    %cl,%dx
	shlw    %cl,%bx
	notw    %bx
	xchgw   %cx,%ax
	movl    $DRCCFG, %edi
	mov     (%edi), %ax
	andw    %bx,%ax
	orw     %dx,%ax
	movw    %ax, (%edi)
	jcxz    cleanup

	decw    %cx
	movl    %ecx,%ebx
	movl    $DRCBENDADR, %edi        /* DRAM ending address register */
	movb    $0xff,%al
	addl	%ebx, %edi
	movb    %al, (%edi)
 /*
  * set control register to NORMAL mode
  */
	movl    $DRCCTL, %esi            /* setup DRAM control register with */
	movb    $0x0,%al                 /* Normal mode value */
	movb    %al, (%esi)
	movl    $CACHELINESZ, %esi       /* address to init read buffer */
	movw    %ax, (%esi)
	jmp     nextbank

cleanup:
	movl    $DRCBENDADR, %edi        /* DRAM ending address register  */
	movw    $4,%cx
	xorw    %ax,%ax
cleanuplp:
	movb   (%edi), %al
	orb     %al,%al
	jz      emptybank

	addb    %ah,%al
	jns     nottoomuch

	movb    $0x7f,%al
nottoomuch:
	movb    %al,%ah
	orb     $0x80,%al
	movb    %al, (%edi)
emptybank:
	incl    %edi
	loop    cleanuplp

#if defined(CFG_SDRAM_CAS_LATENCY_2T) || defined(CFG_SDRAM_CAS_LATENCY_3T)
	/* set the CAS latency now since it is hard to do
	 * when we run from the RAM */
	movl    $DRCTMCTL, %edi          /* DRAM timing register */
	movb    (%edi), %al
#ifdef CFG_SDRAM_CAS_LATENCY_2T
	andb    $0xef, %al
#endif
#ifdef CFG_SDRAM_CAS_LATENCY_3T
	orb     $0x10, %al
#endif
	movb    %al, (%edi)
#endif
	movl    $DRCCTL, %edi            /* DRAM Control register */
	movb    $0x3,%al                 /* Load mode register cmd */
	movb     %al, (%edi)
	movw     %ax, (%esi)


	movl    $DRCCTL, %edi            /* DRAM Control register */
	movb    $0x18,%al                /*  Enable refresh and NORMAL mode */
	movb    %al, (%edi)

	jmp     dram_done

bad_ram:
	xorl    %edx,%edx
	xorl    %edi,%edi
	jmp     bad_reint

dram_done:

	/* readback DRCBENDADR and return the number
	 * of available ram bytes in %eax */

	movl    $DRCBENDADR, %edi        /* DRAM ending address register  */

	movl	(%edi), %eax
	movl	%eax, %ecx
	andl	$0x80000000, %ecx
	jz	bank2
	andl	$0x7f000000, %eax
	shrl	$2, %eax
	movl	%eax, %ebx

bank2: 	movl	(%edi), %eax
	movl	%eax, %ecx
	andl	$0x00800000, %ecx
	jz	bank1
	andl	$0x007f0000, %eax
	shll	$6, %eax
	movl	%eax, %ebx

bank1: 	movl	(%edi), %eax
	movl	%eax, %ecx
	andl	$0x00008000, %ecx
	jz	bank0
	andl	$0x00007f00, %eax
	shll	$14, %eax
	movl	%eax, %ebx

bank0: 	movl	(%edi), %eax
	movl	%eax, %ecx
	andl	$0x00000080, %ecx
	jz	done
	andl	$0x0000007f, %eax
	shll	$22, %eax
	movl	%eax, %ebx

done:	movl	%ebx, %eax

	jmp	*%ebp


#endif /* CONFIG_SC520 */