start.s.svn-base

u-boot for S3c2443 processor

/*
 *  Copyright (C) 1998	Dan Malek <[e-mail]>
 *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
 *  Copyright (C) 2000, 2001,2002 Wolfgang Denk <[e-mail]>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 *  U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
 */
#include <config.h>
#include <mpc8260.h>
#include <version.h>

#define CONFIG_8260 1		/* needed for Linux kernel header files */
#define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/

#include <ppc_asm.tmpl>
#include <ppc_defs.h>

#include <asm/cache.h>
#include <asm/mmu.h>

#ifndef  CONFIG_IDENT_STRING
#define  CONFIG_IDENT_STRING ""
#endif

/* We don't want the  MMU yet.
*/
#undef	MSR_KERNEL
/* Floating Point enable, Machine Check and Recoverable Interr. */
#ifdef DEBUG
#define MSR_KERNEL (MSR_FP|MSR_RI)
#else
#define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
#endif

/*
 * Set up GOT: Global Offset Table
 *
 * Use r14 to access the GOT
 */
	START_GOT
	GOT_ENTRY(_GOT2_TABLE_)
	GOT_ENTRY(_FIXUP_TABLE_)

	GOT_ENTRY(_start)
	GOT_ENTRY(_start_of_vectors)
	GOT_ENTRY(_end_of_vectors)
	GOT_ENTRY(transfer_to_handler)

	GOT_ENTRY(__init_end)
	GOT_ENTRY(_end)
	GOT_ENTRY(__bss_start)
#if defined(CONFIG_HYMOD)
	GOT_ENTRY(environment)
#endif
	END_GOT

/*
 * Version string - must be in data segment because MPC8260 uses the first
 * 256 bytes for the Hard Reset Configuration Word table (see below).
 * Similarly, can't have the U-Boot Magic Number as the first thing in
 * the image - don't know how this will affect the image tools, but I guess
 * I'll find out soon
 */
	.data
	.globl	version_string
version_string:
	.ascii U_BOOT_VERSION
	.ascii " (", __DATE__, " - ", __TIME__, ")"
	.ascii CONFIG_IDENT_STRING, "\0"

/*
 *  Hard Reset Configuration Word (HRCW) table
 *
 *  The Hard Reset Configuration Word (HRCW) sets a number of useful things
 *  such as whether there is an external memory controller, whether the
 *  PowerPC core is disabled (i.e. only the communications processor is
 *  active, accessed by another CPU on the bus), whether using external
 *  arbitration, external bus mode, boot port size, core initial prefix,
 *  internal space base, boot memory space, etc.
 *
 *  These things dictate where the processor begins execution, where the
 *  boot ROM appears in memory, the memory controller setup when access
 *  boot ROM, etc. The HRCW is *extremely* important.
 *
 *  The HRCW is read from the bus during reset. One CPU on the bus will
 *  be a hard reset configuration master, any others will be hard reset
 *  configuration slaves. The master reads eight HRCWs from flash during
 *  reset - the first it uses for itself, the other 7 it communicates to
 *  up to 7 configuration slaves by some complicated mechanism, which is
 *  not really important here.
 *
 *  The configuration master performs 32 successive reads starting at address
 *  0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
 *  bits is read, and always from byte lane D[0-7] (so that port size of the
 *  boot device does not matter). The first four reads form the 32 bit HRCW
 *  for the master itself. The second four reads form the HRCW for the first
 *  slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
 *  concatenating the four bytes, with the first read placed in byte 0 (the
 *  most significant byte), and so on with the fourth read placed in byte 3
 *  (the least significant byte).
 */
#define _HRCW_TABLE_ENTRY(w)		\
	.fill	8,1,(((w)>>24)&0xff);	\
	.fill	8,1,(((w)>>16)&0xff);	\
	.fill	8,1,(((w)>> 8)&0xff);	\
	.fill	8,1,(((w)    )&0xff)
	.text
	.globl	_hrcw_table
_hrcw_table:
	_HRCW_TABLE_ENTRY(CFG_HRCW_MASTER)
	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1)
	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2)
	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3)
	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4)
	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5)
	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6)
	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7)
/*
 *  After configuration, a system reset exception is executed using the
 *  vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
 *  is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
 *  is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
 *  of MSR[IP] is determined by the CIP field in the HRCW.
 *
 *  Other bits in the HRCW set up the Base Address and Port Size in BR0.
 *  This determines the location of the boot ROM (flash or EPROM) in the
 *  processor's address space at boot time. As long as the HRCW is set up
 *  so that we eventually end up executing the code below when the processor
 *  executes the reset exception, the actual values used should not matter.
 *
 *  Once we have got here, the address mask in OR0 is cleared so that the
 *  bottom 32K of the boot ROM is effectively repeated all throughout the
 *  processor's address space, after which we can jump to the absolute
 *  address at which the boot ROM was linked at compile time, and proceed
 *  to initialise the memory controller without worrying if the rug will be
 *  pulled out from under us, so to speak (it will be fine as long as we
 *  configure BR0 with the same boot ROM link address).
 */
	. = EXC_OFF_SYS_RESET

	.globl	_start
_start:
	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH*/
	nop
	b	boot_cold

	. = EXC_OFF_SYS_RESET + 0x10

	.globl	_start_warm
_start_warm:
	li	r21, BOOTFLAG_WARM	/* Software reboot		*/
	b	boot_warm

boot_cold:
#if defined(CONFIG_MPC8260ADS)
	lis	r3, CFG_DEFAULT_IMMR@h
	nop
	lwz	r4, 0(r3)
	nop
	rlwinm	r4, r4, 0, 8, 5
	nop
	oris	r4, r4, 0x0200
	nop
	stw	r4, 0(r3)
	nop
#endif /* CONFIG_MPC8260ADS */
boot_warm:
	mfmsr	r5			/* save msr contents		*/

#if defined(CONFIG_COGENT)
	/* this is what the cogent EPROM does */
	li	r0, 0
	mtmsr	r0
	isync
	bl	cogent_init_8260
#endif	/* CONFIG_COGENT */

#if defined(CFG_DEFAULT_IMMR)
	lis	r3, CFG_IMMR@h
	ori	r3, r3, CFG_IMMR@l
	lis	r4, CFG_DEFAULT_IMMR@h
	stw	r3, 0x1A8(r4)
#endif /* CFG_DEFAULT_IMMR */

	/* Initialise the MPC8260 processor core			*/
	/*--------------------------------------------------------------*/

	bl	init_8260_core

#ifndef CFG_RAMBOOT
	/* When booting from ROM (Flash or EPROM), clear the		*/
	/* Address Mask in OR0 so ROM appears everywhere		*/
	/*--------------------------------------------------------------*/

	lis	r3, (CFG_IMMR+IM_REGBASE)@h
	lwz	r4, IM_OR0@l(r3)
	li	r5, 0x7fff
	and	r4, r4, r5
	stw	r4, IM_OR0@l(r3)

	/* Calculate absolute address in FLASH and jump there		*/
	/*--------------------------------------------------------------*/

	lis	r3, CFG_MONITOR_BASE@h
	ori	r3, r3, CFG_MONITOR_BASE@l
	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
	mtlr	r3
	blr

in_flash:
#endif	/* CFG_RAMBOOT */

	/* initialize some things that are hard to access from C	*/
	/*--------------------------------------------------------------*/

	lis	r3, CFG_IMMR@h		/* set up stack in internal DPRAM */
	ori	r1, r3, CFG_INIT_SP_OFFSET
	li	r0, 0			/* Make room for stack frame header and	*/
	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/

	/* let the C-code set up the rest				*/
	/*								*/
	/* Be careful to keep code relocatable !			*/
	/*--------------------------------------------------------------*/

	GET_GOT			/* initialize GOT access		*/

	/* r3: IMMR */
	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/

#ifdef DEBUG
	bl	init_debug	/* set up debugging stuff		*/
#endif

	mr	r3, r21
	/* r3: BOOTFLAG */
	bl	board_init_f	/* run 1st part of board init code (in Flash)*/

/*
 * Vector Table
 */

	.globl	_start_of_vectors
_start_of_vectors:

/* Machine check */
	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)

/* Data Storage exception. */
	STD_EXCEPTION(0x300, DataStorage, UnknownException)

/* Instruction Storage exception. */
	STD_EXCEPTION(0x400, InstStorage, UnknownException)

/* External Interrupt exception. */
	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)

/* Alignment exception. */
	. = 0x600
Alignment:
	EXCEPTION_PROLOG
	mfspr	r4,DAR
	stw	r4,_DAR(r21)
	mfspr	r5,DSISR
	stw	r5,_DSISR(r21)
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_Alignment:
	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

/* Program check exception */
	. = 0x700
ProgramCheck:
	EXCEPTION_PROLOG
	addi	r3,r1,STACK_FRAME_OVERHEAD
	li	r20,MSR_KERNEL
	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
	lwz	r6,GOT(transfer_to_handler)
	mtlr	r6
	blrl
.L_ProgramCheck:
	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
	.long	int_return - _start + EXC_OFF_SYS_RESET

	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)

	/* I guess we could implement decrementer, and may have
	 * to someday for timekeeping.
	 */
	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)

	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
	STD_EXCEPTION(0xc00, SystemCall, UnknownException)
	STD_EXCEPTION(0xd00, SingleStep, UnknownException)

	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)

	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
#ifdef DEBUG
	. = 0x1300
	/*
	 * This exception occurs when the program counter matches the
	 * Instruction Address Breakpoint Register (IABR).
	 *
	 * I want the cpu to halt if this occurs so I can hunt around
	 * with the debugger and look at things.
	 *
	 * When DEBUG is defined, both machine check enable (in the MSR)
	 * and checkstop reset enable (in the reset mode register) are
	 * turned off and so a checkstop condition will result in the cpu
	 * halting.
	 *
	 * I force the cpu into a checkstop condition by putting an illegal
	 * instruction here (at least this is the theory).
	 *
	 * well - that didnt work, so just do an infinite loop!
	 */
1:	b	1b
#else
	STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
#endif
	STD_EXCEPTION(0x1400, SMI, UnknownException)

	STD_EXCEPTION(0x1500, Trap_15, UnknownException)
	STD_EXCEPTION(0x1600, Trap_16, UnknownException)
	STD_EXCEPTION(0x1700, Trap_17, UnknownException)
	STD_EXCEPTION(0x1800, Trap_18, UnknownException)
	STD_EXCEPTION(0x1900, Trap_19, UnknownException)
	STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
	STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
	STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
	STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
	STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
	STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
	STD_EXCEPTION(0x2000, Trap_20, UnknownException)
	STD_EXCEPTION(0x2100, Trap_21, UnknownException)
	STD_EXCEPTION(0x2200, Trap_22, UnknownException)
	STD_EXCEPTION(0x2300, Trap_23, UnknownException)
	STD_EXCEPTION(0x2400, Trap_24, UnknownException)
	STD_EXCEPTION(0x2500, Trap_25, UnknownException)
	STD_EXCEPTION(0x2600, Trap_26, UnknownException)
	STD_EXCEPTION(0x2700, Trap_27, UnknownException)
	STD_EXCEPTION(0x2800, Trap_28, UnknownException)
	STD_EXCEPTION(0x2900, Trap_29, UnknownException)
	STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
	STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
	STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
	STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
	STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
	STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)


	.globl	_end_of_vectors
_end_of_vectors:

	. = 0x3000

/*
 * This code finishes saving the registers to the exception frame
 * and jumps to the appropriate handler for the exception.
 * Register r21 is pointer into trap frame, r1 has new stack pointer.
 */
	.globl	transfer_to_handler
transfer_to_handler:
	stw	r22,_NIP(r21)
	lis	r22,MSR_POW@h
	andc	r23,r23,r22
	stw	r23,_MSR(r21)
	SAVE_GPR(7, r21)
	SAVE_4GPRS(8, r21)
	SAVE_8GPRS(12, r21)
	SAVE_8GPRS(24, r21)
	mflr	r23
	andi.	r24,r23,0x3f00		/* get vector offset */
	stw	r24,TRAP(r21)
	li	r22,0
	stw	r22,RESULT(r21)
	lwz	r24,0(r23)		/* virtual address of handler */
	lwz	r23,4(r23)		/* where to go when done */
	mtspr	SRR0,r24
	mtspr	SRR1,r20
	mtlr	r23
	SYNC
	rfi				/* jump to handler, enable MMU */

int_return:
	mfmsr	r28		/* Disable interrupts */
	li	r4,0
	ori	r4,r4,MSR_EE
	andc	r28,r28,r4
	SYNC			/* Some chip revs need this... */
	mtmsr	r28
	SYNC
	lwz	r2,_CTR(r1)
	lwz	r0,_LINK(r1)
	mtctr	r2
	mtlr	r0
	lwz	r2,_XER(r1)
	lwz	r0,_CCR(r1)
	mtspr	XER,r2
	mtcrf	0xFF,r0
	REST_10GPRS(3, r1)
	REST_10GPRS(13, r1)
	REST_8GPRS(23, r1)
	REST_GPR(31, r1)
	lwz	r2,_NIP(r1)	/* Restore environment */
	lwz	r0,_MSR(r1)
	mtspr	SRR0,r2
	mtspr	SRR1,r0
	lwz	r0,GPR0(r1)
	lwz	r2,GPR2(r1)
	lwz	r1,GPR1(r1)
	SYNC
	rfi

#if defined(CONFIG_COGENT)

/*
 * This code initialises the MPC8260 processor core
 * (conforms to PowerPC 603e spec)
 */

	.globl	cogent_init_8260
cogent_init_8260:

	/* Taken from page 14 of CMA282 manual				*/
	/*--------------------------------------------------------------*/

	lis	r4, (CFG_IMMR+IM_REGBASE)@h
	lis	r3, CFG_IMMR@h
	stw	r3, IM_IMMR@l(r4)
	lwz	r3, IM_IMMR@l(r4)
	stw	r3, 0(r0)
	lis	r3, CFG_SYPCR@h
	ori	r3, r3, CFG_SYPCR@l
	stw	r3, IM_SYPCR@l(r4)
	lwz	r3, IM_SYPCR@l(r4)
	stw	r3, 4(r0)
	lis	r3, CFG_SCCR@h
	ori	r3, r3, CFG_SCCR@l
	stw	r3, IM_SCCR@l(r4)
	lwz	r3, IM_SCCR@l(r4)
	stw	r3, 8(r0)

	/* the rest of this was disassembled from the			*/
	/* EPROM code that came with my CMA282 CPU module		*/
	/*--------------------------------------------------------------*/

	lis	r1, 0x1234
	ori	r1, r1, 0x5678
	stw	r1, 0x20(r0)
	lwz	r1, 0x20(r0)
	stw	r1, 0x24(r0)
	lwz	r1, 0x24(r0)
	lis	r3, 0x0e80
	ori	r3, r3, 0
	stw	r1, 4(r3)
	lwz	r1, 4(r3)

	/* Done!							*/
	/*--------------------------------------------------------------*/

	blr

#endif	/* CONFIG_COGENT */

/*
 * This code initialises the MPC8260 processor core
 * (conforms to PowerPC 603e spec)
 * Note: expects original MSR contents to be in r5.
 */

	.globl	init_8260_core
init_8260_core:

	/* Initialize machine status; enable machine check interrupt	*/
	/*--------------------------------------------------------------*/

	li	r3, MSR_KERNEL		/* Set ME and RI flags */
	rlwimi	r3, r5, 0, 25, 25	/* preserve IP bit set by HRCW */
#ifdef DEBUG
	rlwimi	r3, r5, 0, 21, 22	/* debugger might set SE & BE bits */
#endif
	SYNC				/* Some chip revs need this... */
	mtmsr	r3
	SYNC
	mtspr	SRR1, r3		/* Make SRR1 match MSR */

	/* Initialise the SYPCR early, and reset the watchdog (if req)	*/
	/*--------------------------------------------------------------*/

	lis	r3, (CFG_IMMR+IM_REGBASE)@h