405gp_pci.c.svn-base

u-boot for S3c2443 processor

		 * Write the 405GP PCI Configuration regs.
		 * Enable 405GP to be a master on the PCI bus (PMM).
		 * Enable 405GP to act as a PCI memory target (PTM).
		 *--------------------------------------------------------------------------*/
		pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
		pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
				      PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
	}
#endif

#if defined(CONFIG_405EP) /* on ppc405ep vendor id is not set */
	pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, 0x1014); /* IBM */
#endif

	/*
	 * Set HCE bit (Host Configuration Enabled)
	 */
	pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
	pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));

#ifdef CONFIG_PCI_PNP
	/*--------------------------------------------------------------------------+
	 * Scan the PCI bus and configure devices found.
	 *--------------------------------------------------------------------------*/
#if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
	if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
#endif
	{
#ifdef CONFIG_PCI_SCAN_SHOW
		printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif

		hose->last_busno = pci_hose_scan(hose);
	}
#endif  /* CONFIG_PCI_PNP */

}

/*
 * drivers/pci.c skips every host bridge but the 405GP since it could
 * be set as an Adapter.
 *
 * I (Andrew May) don't know what we should do here, but I don't want
 * the auto setup of a PCI device disabling what is done pci_405gp_init
 * as has happened before.
 */
void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
			    struct pci_config_table *entry)
{
#ifdef DEBUG
	printf("405gp_setup_bridge\n");
#endif
}

/*
 *
 */

void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
	unsigned char int_line = 0xff;

	/*
	 * Write pci interrupt line register (cpci405 specific)
	 */
	switch (PCI_DEV(dev) & 0x03)
	{
	case 0:
		int_line = 27 + 2;
		break;
	case 1:
		int_line = 27 + 3;
		break;
	case 2:
		int_line = 27 + 0;
		break;
	case 3:
		int_line = 27 + 1;
		break;
	}

	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}

void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
			 struct pci_config_table *entry)
{
	unsigned int cmdstat = 0;

	pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io);

	/* always enable io space on vga boards */
	pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
	cmdstat |= PCI_COMMAND_IO;
	pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
}

#if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405))

/*
 *As is these functs get called out of flash Not a horrible
 *thing, but something to keep in mind. (no statics?)
 */
static struct pci_config_table pci_405gp_config_table[] = {
/*if VendID is 0 it terminates the table search (ie Walnut)*/
#ifdef CFG_PCI_SUBSYS_VENDORID
	{CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
#endif
	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},

	{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},

	{ }
};

static struct pci_controller hose = {
	fixup_irq: pci_405gp_fixup_irq,
	config_table: pci_405gp_config_table,
};

void pci_init_board(void)
{
	/*we want the ptrs to RAM not flash (ie don't use init list)*/
	hose.fixup_irq    = pci_405gp_fixup_irq;
	hose.config_table = pci_405gp_config_table;
	pci_405gp_init(&hose);
}

#endif

#endif /* CONFIG_PCI */

#endif /* CONFIG_405GP */

/*-----------------------------------------------------------------------------+
 * CONFIG_440
 *-----------------------------------------------------------------------------*/
#if defined(CONFIG_440) && defined(CONFIG_PCI)

static struct pci_controller ppc440_hose = {0};


void pci_440_init (struct pci_controller *hose)
{
	int reg_num = 0;
	unsigned long strap;

	/*--------------------------------------------------------------------------+
	 * The PCI initialization sequence enable bit must be set ... if not abort
	 * pci setup since updating the bit requires chip reset.
	 *--------------------------------------------------------------------------*/
#if defined (CONFIG_440_GX)
	mfsdr(sdr_sdstp1,strap);
	if ( (strap & 0x00010000) == 0 ){
		printf("PCI: SDR0_STRP1[PISE] not set.\n");
		printf("PCI: Configuration aborted.\n");
		return;
	}
#else
	strap = mfdcr(cpc0_strp1);
	if( (strap & 0x00040000) == 0 ){
		printf("PCI: CPC0_STRP1[PISE] not set.\n");
		printf("PCI: Configuration aborted.\n");
		return;
	}
#endif
	/*--------------------------------------------------------------------------+
	 * PCI controller init
	 *--------------------------------------------------------------------------*/
	hose->first_busno = 0;
	hose->last_busno = 0xff;

	pci_set_region(hose->regions + reg_num++,
		       0x00000000,
			   PCIX0_IOBASE,
			   0x10000,
			   PCI_REGION_IO);

	pci_set_region(hose->regions + reg_num++,
		       CFG_PCI_TARGBASE,
			   CFG_PCI_MEMBASE,
			   0x10000000,
			   PCI_REGION_MEM );
	hose->region_count = reg_num;

	pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);

#if defined(CFG_PCI_PRE_INIT)
    /* Let board change/modify hose & do initial checks */
    if( pci_pre_init (hose) == 0 ){
	printf("PCI: Board-specific initialization failed.\n");
	printf("PCI: Configuration aborted.\n");
	return;
    }
#endif

	pci_register_hose( hose );

	/*--------------------------------------------------------------------------+
	 * PCI target init
	 *--------------------------------------------------------------------------*/
#if defined(CFG_PCI_TARGET_INIT)
	pci_target_init(hose);                /* Let board setup pci target */
#else
    out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
    out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_ID );
    out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */
#endif

#if defined(CONFIG_440_GX)
	out32r( PCIX0_BRDGOPT1, 0x04000060 );               /* PLB Rq pri highest   */
	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1  */
#else
	out32r( PCIX0_BRDGOPT1, 0x10000060 );               /* PLB Rq pri highest   */
	out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config   */
#endif

	/*--------------------------------------------------------------------------+
	 * PCI master init: default is one 256MB region for PCI memory:
	 * 0x3_00000000 - 0x3_0FFFFFFF  ==> CFG_PCI_MEMBASE
	 *--------------------------------------------------------------------------*/
#if defined(CFG_PCI_MASTER_INIT)
	pci_master_init(hose);          /* Let board setup pci master */
#else
	out32r( PCIX0_POM0SA, 0 ); /* disable */
	out32r( PCIX0_POM1SA, 0 ); /* disable */
	out32r( PCIX0_POM2SA, 0 ); /* disable */
	out32r( PCIX0_POM0LAL, 0x00000000 );
	out32r( PCIX0_POM0LAH, 0x00000003 );
	out32r( PCIX0_POM0PCIAL, CFG_PCI_MEMBASE );
	out32r( PCIX0_POM0PCIAH, 0x00000000 );
	out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
    out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 );
#endif

	/*--------------------------------------------------------------------------+
	 * PCI host configuration -- we don't make any assumptions here ... the
     * _board_must_indicate_ what to do -- there's just too many runtime
     * scenarios in environments like cPCI, PPMC, etc. to make a determination
     * based on hard-coded values or state of arbiter enable.
	 *--------------------------------------------------------------------------*/
    if( is_pci_host(hose) ){
#ifdef CONFIG_PCI_SCAN_SHOW
	printf("PCI:   Bus Dev VenId DevId Class Int\n");
#endif
	out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER);
	hose->last_busno = pci_hose_scan(hose);
    }
}


void pci_init_board(void)
{
	pci_440_init (&ppc440_hose);
}

#endif /* CONFIG_440 & CONFIG_PCI */