i2c.c.svn-base

u-boot for S3c2443 processor

		PRINTD(("[I2C] Formatting addresses...\n"));
		if (flags & I2CF_ENABLE_SECONDARY) {
			txbd->length = size + 2;  /* Length of msg + dest addr */
			txbd->addr[0] = address << 1;
			txbd->addr[1] = secondary_address;
			i = 2;
		} else {
			txbd->length = size + 1;  /* Length of msg + dest addr */
			txbd->addr[0] = address << 1;  /* Write dest addr to BD */
			i = 1;
		}
	} else {
		txbd->length = size;  /* Length of message */
		i = 0;
	}

	/* set up txbd */
	txbd->status = BD_SC_READY;
	if (flags & I2CF_START_COND)
	  txbd->status |= BD_I2C_TX_START;
	if (flags & I2CF_STOP_COND)
	  txbd->status |= BD_SC_LAST | BD_SC_WRAP;

	/* Copy data to send into buffer */
	PRINTD(("[I2C] copy data...\n"));
	for(j = 0; j < size; i++, j++)
	  txbd->addr[i] = dataout[j];

	PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
		   txbd->length,
		   txbd->status,
		   txbd->addr[0],
		   txbd->addr[1]));

	/* advance state */
	state->tx_buf += txbd->length;
	state->tx_space -= txbd->length;
	state->tx_idx++;
	state->txbd = (void*)(txbd + 1);

	return 0;
}

static int
i2c_receive(i2c_state_t *state,
	    unsigned char address,
	    unsigned char secondary_address,
	    unsigned int flags,
	    unsigned short size_to_expect,
	    unsigned char *datain)
{
	volatile I2C_BD *rxbd, *txbd;

	PRINTD(("[I2C] i2c_receive %02d %02d %02d\n", address, secondary_address, flags));

	/* Expected to receive too much */
	if (size_to_expect > I2C_RXTX_LEN)
	  return I2CERR_MSG_TOO_LONG;

	/* no more free bds */
	if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
		 || state->tx_space < 2)
	  return I2CERR_NO_BUFFERS;

	rxbd = (I2C_BD *)state->rxbd;
	txbd = (I2C_BD *)state->txbd;

	PRINTD(("[I2C] rxbd = %08x\n", (int)rxbd));
	PRINTD(("[I2C] txbd = %08x\n", (int)txbd));

	txbd->addr = state->tx_buf;

	/* set up TXBD for destination address */
	if (flags & I2CF_ENABLE_SECONDARY) {
		txbd->length = 2;
		txbd->addr[0] = address << 1;   /* Write data */
		txbd->addr[1] = secondary_address;  /* Internal address */
		txbd->status = BD_SC_READY;
	} else {
		txbd->length = 1 + size_to_expect;
		txbd->addr[0] = (address << 1) | 0x01;
		txbd->status = BD_SC_READY;
		memset(&txbd->addr[1], 0, txbd->length);
	}

	/* set up rxbd for reception */
	rxbd->status = BD_SC_EMPTY;
	rxbd->length = size_to_expect;
	rxbd->addr = datain;

	txbd->status |= BD_I2C_TX_START;
	if (flags & I2CF_STOP_COND) {
		txbd->status |= BD_SC_LAST | BD_SC_WRAP;
		rxbd->status |= BD_SC_WRAP;
	}

	PRINTD(("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
		   txbd->length,
		   txbd->status,
		   txbd->addr[0],
		   txbd->addr[1]));
	PRINTD(("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
		   rxbd->length,
		   rxbd->status,
		   rxbd->addr[0],
		   rxbd->addr[1]));

	/* advance state */
	state->tx_buf += txbd->length;
	state->tx_space -= txbd->length;
	state->tx_idx++;
	state->txbd = (void*)(txbd + 1);
	state->rx_idx++;
	state->rxbd = (void*)(rxbd + 1);

	return 0;
}


static int i2c_doio(i2c_state_t *state)
{
	volatile immap_t *immap = (immap_t *)CFG_IMMR ;
	volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
	volatile i2c8xx_t *i2c	= (i2c8xx_t *)&immap->im_i2c;
	volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
	volatile I2C_BD *txbd, *rxbd;
	volatile int j = 0;

	PRINTD(("[I2C] i2c_doio\n"));

#ifdef CFG_I2C_UCODE_PATCH
	iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
#endif

	if (state->tx_idx <= 0 && state->rx_idx <= 0) {
		PRINTD(("[I2C] No I/O is queued\n"));
		return I2CERR_QUEUE_EMPTY;
	}

	iip->iic_rbptr = iip->iic_rbase;
	iip->iic_tbptr = iip->iic_tbase;

	/* Enable I2C */
	PRINTD(("[I2C] Enabling I2C...\n"));
	i2c->i2c_i2mod |= 0x01;

	/* Begin transmission */
	i2c->i2c_i2com |= 0x80;

	/* Loop until transmit & receive completed */

	if (state->tx_idx > 0) {
		txbd = ((I2C_BD*)state->txbd) - 1;
		PRINTD(("[I2C] Transmitting...(txbd=0x%08lx)\n", (ulong)txbd));
		while((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
			if (ctrlc()) {
				return (-1);
			}
			__asm__ __volatile__ ("eieio");
		}
	}

	if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
		rxbd = ((I2C_BD*)state->rxbd) - 1;
		PRINTD(("[I2C] Receiving...(rxbd=0x%08lx)\n", (ulong)rxbd));
		while((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
			if (ctrlc()) {
				return (-1);
			}
			__asm__ __volatile__ ("eieio");
		}
	}

	/* Turn off I2C */
	i2c->i2c_i2mod &= ~0x01;

	if (state->err_cb != NULL) {
		int n, i, b;

		/*
		 * if we have an error callback function, look at the
		 * error bits in the bd status and pass them back
		 */

		if ((n = state->tx_idx) > 0) {
			for (i = 0; i < n; i++) {
				txbd = ((I2C_BD*)state->txbd) - (n - i);
				if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
					(*state->err_cb)(I2CECB_TX_ERR|b, i);
			}
		}

		if ((n = state->rx_idx) > 0) {
			for (i = 0; i < n; i++) {
				rxbd = ((I2C_BD*)state->rxbd) - (n - i);
				if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
					(*state->err_cb)(I2CECB_RX_ERR|b, i);
			}
		}

		if (j >= TOUT_LOOP)
			(*state->err_cb)(I2CECB_TIMEOUT, 0);
	}

	return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
}

static int had_tx_nak;

static void
i2c_test_callback(int flags, int xnum)
{
	if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
		had_tx_nak = 1;
}

int i2c_probe(uchar chip)
{
	i2c_state_t state;
  	int rc;
	uchar buf[1];

	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

	i2c_newio(&state);

	state.err_cb = i2c_test_callback;
	had_tx_nak = 0;

	rc = i2c_receive(&state, chip, 0, I2CF_START_COND|I2CF_STOP_COND, 1, buf);

	if (rc != 0)
		return (rc);

	rc = i2c_doio(&state);

	if ((rc != 0) && (rc != I2CERR_TIMEOUT))
		return (rc);

	return (had_tx_nak);
}

int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
	DECLARE_GLOBAL_DATA_PTR;

	i2c_state_t state;
	uchar xaddr[4];
	int rc;

#ifdef CONFIG_LWMON
	WATCHDOG_RESET();
#endif

	xaddr[0] = (addr >> 24) & 0xFF;
	xaddr[1] = (addr >> 16) & 0xFF;
	xaddr[2] = (addr >>  8) & 0xFF;
	xaddr[3] =  addr        & 0xFF;

#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones like
	 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
	 * extra bits end up in the "chip address" bit slots.  This makes
	 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to still
	 * be one byte because the extra address bits are hidden in the
	 * chip address.
	 */
	 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif

	i2c_newio(&state);

	rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
	if (rc != 0) {
		if (gd->have_console)
			printf("i2c_read: i2c_send failed (%d)\n", rc);
		return 1;
	}

	rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
	if (rc != 0) {
		if (gd->have_console)
			printf("i2c_read: i2c_receive failed (%d)\n", rc);
		return 1;
	}

	rc = i2c_doio(&state);
	if (rc != 0) {
		if (gd->have_console)
			printf("i2c_read: i2c_doio failed (%d)\n", rc);
		return 1;
	}
	return 0;
}

int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
	DECLARE_GLOBAL_DATA_PTR;

	i2c_state_t state;
	uchar xaddr[4];
	int rc;

	xaddr[0] = (addr >> 24) & 0xFF;
	xaddr[1] = (addr >> 16) & 0xFF;
	xaddr[2] = (addr >>  8) & 0xFF;
	xaddr[3] =  addr        & 0xFF;

#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
	/*
	 * EEPROM chips that implement "address overflow" are ones like
	 * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
	 * extra bits end up in the "chip address" bit slots.  This makes
	 * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
	 *
	 * Note that we consider the length of the address field to still
	 * be one byte because the extra address bits are hidden in the
	 * chip address.
	 */
	 chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
#endif

	i2c_newio(&state);

	rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen, &xaddr[4-alen]);
	if (rc != 0) {
		if (gd->have_console)
			printf("i2c_write: first i2c_send failed (%d)\n", rc);
		return 1;
	}

	rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
	if (rc != 0) {
		if (gd->have_console)
			printf("i2c_write: second i2c_send failed (%d)\n", rc);
		return 1;
	}

	rc = i2c_doio(&state);
	if (rc != 0) {
		if (gd->have_console)
			printf("i2c_write: i2c_doio failed (%d)\n", rc);
		return 1;
	}
	return 0;
}

uchar
i2c_reg_read(uchar i2c_addr, uchar reg)
{
	char buf;

	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

	i2c_read(i2c_addr, reg, 1, &buf, 1);

	return (buf);
}

void
i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
{
	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);

	i2c_write(i2c_addr, reg, 1, &val, 1);
}

#endif	/* CONFIG_HARD_I2C */